Searched full:serdes2 (Results 1 – 6 of 6) sorted by relevance
97 <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */
130 u32 srds2cr0; /* 0x.0f40 - SerDes2 Control Register 0 */131 u32 srds2cr1; /* 0x.0f44 - SerDes2 Control Register 0 */
895 &serdes2 {896 assigned-clocks = <&serdes2 CDNS_SIERRA_PLL_CMNLC>;
668 idle-states = <1>, <1>; /* USB0 to SERDES3, USB1 to SERDES2 */726 &serdes2 {
750 idle-states = <1>, <1>; /* USB0 to SERDES3, USB1 to SERDES2 */808 &serdes2 {
53 <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */735 serdes2: serdes@5020000 { label