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/Linux-v5.10/Documentation/devicetree/bindings/phy/
Dphy-ocelot-serdes.txt1 Microsemi Ocelot SerDes muxing driver
5 space for setting up the SerDes to switch port muxing.
7 A SerDes X can be "muxed" to work with switch port Y or Z for example.
8 One specific SerDes can also be used as a PCIe interface.
10 Hence, a SerDes represents an interface, be it an Ethernet or a PCIe one.
12 There are two kinds of SerDes: SERDES1G supports 10/100Mbps in
24 - compatible: should be "mscc,vsc7514-serdes"
27 SerDes macro. The second defines the macro to use. They are
28 defined in dt-bindings/phy/phy-ocelot-serdes.h
32 serdes: serdes {
[all …]
Dti,phy-am654-serdes.txt1 TI AM654 SERDES
4 - compatible: Should be "ti,phy-am654-serdes"
9 include/dt-bindings/phy/phy.h) and the 2nd cell should be the serdes
21 - clocks: List of clock-specifiers representing the input to the SERDES.
25 SERDES. Should have 3 items for CMU reference clock,
34 The following macros are defined in dt-bindings/phy/phy-am654-serdes.h
36 specifying the clocks created by SERDES.
60 serdes0: serdes@900000 {
61 compatible = "ti,phy-am654-serdes";
63 reg-names = "serdes";
[all …]
Dti,phy-j721e-wiz.yaml8 title: TI J721E WIZ (SERDES Wrapper)
63 If GPIO is active, lane 0 and lane 1 of SERDES will be swapped to
81 the SERDES.
106 provided by the SERDES.
148 "^serdes@[0-9a-f]+$":
151 WIZ node should have '1' subnode for the SERDES. It could be either
152 Sierra SERDES or Torrent SERDES. Sierra SERDES should follow the
155 Torrent SERDES should follow the bindings specified in
220 serdes@5000000 {
222 reg-names = "serdes";
Dxlnx,zynqmp-psgtr.yaml61 - description: SERDES registers block
66 - const: serdes
99 reg-names = "serdes", "siou";
/Linux-v5.10/arch/arm64/boot/dts/amd/
Damd-seattle-xgbe-b.dtsi40 <0 0xe1240800 0 0x00400>, /* SERDES RX/TX0 */
41 <0 0xe1250000 0 0x00060>, /* SERDES IR 1/2 */
42 <0 0xe12500f8 0 0x00004>; /* SERDES IR 2/2 */
48 amd,serdes-blwc = <1>, <1>, <0>;
49 amd,serdes-cdr-rate = <2>, <2>, <7>;
50 amd,serdes-pq-skew = <10>, <10>, <18>;
51 amd,serdes-tx-amp = <0>, <0>, <0>;
52 amd,serdes-dfe-tap-config = <3>, <3>, <3>;
53 amd,serdes-dfe-tap-enable = <0>, <0>, <7>;
66 <0 0xe1240c00 0 0x00400>, /* SERDES RX/TX1 */
[all …]
/Linux-v5.10/Documentation/devicetree/bindings/net/
Damd-xgbe.txt8 - SerDes Rx/Tx registers
9 - SerDes integration registers (1/2)
10 - SerDes integration registers (2/2)
43 - amd,serdes-blwc: Baseline wandering correction enablement
46 - amd,serdes-cdr-rate: CDR rate speed selection
47 - amd,serdes-pq-skew: PQ (data sampling) skew
48 - amd,serdes-tx-amp: TX amplitude boost
49 - amd,serdes-dfe-tap-config: DFE taps available to run
50 - amd,serdes-dfe-tap-enable: DFE taps to enable
70 amd,serdes-blwc = <1>, <1>, <0>;
[all …]
Dhisilicon-hns-dsaf.txt17 The second region is SerDes base register and size(optional, only used when
18 serdes-syscon in port node does not exist). It is recommended using
19 serdes-syscon rather than this address.
40 - serdes-syscon: is syscon handle for SerDes register.
81 serdes-syscon = <&serdes>;
87 serdes-syscon = <&serdes>;
/Linux-v5.10/drivers/phy/mscc/
Dphy-ocelot-serdes.c3 * SerDes PHY driver for Microsemi Ocelot
19 #include <dt-bindings/phy/phy-ocelot-serdes.h>
60 static int serdes_init_s6g(struct regmap *regmap, u8 serdes, int mode) in serdes_init_s6g() argument
89 ret = serdes_update_mcb_s6g(regmap, serdes); in serdes_init_s6g()
146 ret = serdes_commit_mcb_s6g(regmap, serdes); in serdes_init_s6g()
222 ret = serdes_commit_mcb_s6g(regmap, serdes); in serdes_init_s6g()
230 ret = serdes_commit_mcb_s6g(regmap, serdes); in serdes_init_s6g()
244 ret = serdes_commit_mcb_s6g(regmap, serdes); in serdes_init_s6g()
292 static int serdes_init_s1g(struct regmap *regmap, u8 serdes) in serdes_init_s1g() argument
296 ret = serdes_update_mcb_s1g(regmap, serdes); in serdes_init_s1g()
[all …]
DKconfig7 tristate "SerDes PHY driver for Microsemi Ocelot"
12 Enable this for supporting SerDes muxing with Microsemi Ocelot.
/Linux-v5.10/drivers/net/ethernet/sfc/
Denum.h17 * @LOOPBACK_XAUI: loopback within BPX before XAUI serdes
21 * @LOOPBACK_XFI: loopback within BPX before XFI serdes
22 * @LOOPBACK_XAUI_FAR: loopback within BPX after XAUI serdes
25 * @LOOPBACK_XFI_FAR: loopback after XFI serdes
32 * @LOOPBACK_XAUI_WS: wireside loopback within BPX within XAUI serdes
33 * @LOOPBACK_XAUI_WS_FAR: wireside loopback within BPX including XAUI serdes
34 * @LOOPBACK_XAUI_WS_NEAR: wireside loopback within BPX excluding XAUI serdes
36 * @LOOPBACK_XFI_WS: wireside loopback excluding XFI serdes
37 * @LOOPBACK_XFI_WS_FAR: wireside loopback including XFI serdes
/Linux-v5.10/drivers/net/ethernet/sfc/falcon/
Denum.h17 * @LOOPBACK_XAUI: loopback within BPX before XAUI serdes
21 * @LOOPBACK_XFI: loopback within BPX before XFI serdes
22 * @LOOPBACK_XAUI_FAR: loopback within BPX after XAUI serdes
25 * @LOOPBACK_XFI_FAR: loopback after XFI serdes
32 * @LOOPBACK_XAUI_WS: wireside loopback within BPX within XAUI serdes
33 * @LOOPBACK_XAUI_WS_FAR: wireside loopback within BPX including XAUI serdes
34 * @LOOPBACK_XAUI_WS_NEAR: wireside loopback within BPX excluding XAUI serdes
36 * @LOOPBACK_XFI_WS: wireside loopback excluding XFI serdes
37 * @LOOPBACK_XFI_WS_FAR: wireside loopback including XFI serdes
/Linux-v5.10/drivers/phy/marvell/
DKconfig36 shared serdes PHYs on Marvell Armada 3700. Its serdes lanes can be
55 shared serdes PHYs on Marvell Armada 38x. Its serdes lanes can be
66 shared serdes PHYs on Marvell Armada 7k/8k (in the CP110). Its serdes
/Linux-v5.10/drivers/net/ethernet/stmicro/stmmac/
Ddwmac-intel.h11 /* SERDES Register */
15 /* SERDES defines */
17 #define SERDES_RST BIT(2) /* Serdes Reset */
18 #define SERDES_PWR_ST_MASK GENMASK(6, 4) /* Serdes Power state*/
/Linux-v5.10/arch/mips/boot/dts/mscc/
Docelot_pcb120.dts8 #include <dt-bindings/phy/phy-ocelot-serdes.h>
90 phys = <&serdes 4 SERDES1G(2)>;
96 phys = <&serdes 5 SERDES1G(5)>;
102 phys = <&serdes 6 SERDES1G(3)>;
108 phys = <&serdes 9 SERDES1G(4)>;
/Linux-v5.10/drivers/phy/ti/
DKconfig25 tristate "TI AM654 SERDES support"
33 This option enables support for TI AM654 SerDes PHY used for
37 tristate "TI J721E WIZ (SERDES Wrapper) support"
47 SoC. WIZ is a serdes wrapper used to configure some of the input
48 signals to the SERDES (Sierra/Torrent). This driver configures
/Linux-v5.10/include/linux/bcma/
Dbcma_driver_pci.h78 #define BCMA_CORE_PCI_MDIODATA_DEV_ADDR 0x0 /* dev address for serdes */
79 #define BCMA_CORE_PCI_MDIODATA_BLK_ADDR 0x1F /* blk address for serdes */
80 #define BCMA_CORE_PCI_MDIODATA_DEV_PLL 0x1d /* SERDES PLL Dev */
81 #define BCMA_CORE_PCI_MDIODATA_DEV_TX 0x1e /* SERDES TX Dev */
82 #define BCMA_CORE_PCI_MDIODATA_DEV_RX 0x1f /* SERDES RX Dev */
126 #define BCMA_CORE_PCI_PLP_SERDESCTRLOVRDREG 0x230 /* SERDES Control Override */
157 /* SERDES RX registers */
165 /* SERDES PLL registers */
187 /* MDIO devices (SERDES modules) */
/Linux-v5.10/arch/arm64/boot/dts/marvell/
Dcn9132-db.dts108 /* Generic PHY, providing serdes lanes */
158 /* Generic PHY, providing serdes lanes */
168 /* Generic PHY, providing serdes lanes */
177 /* Generic PHY, providing serdes lanes */
219 /* Generic PHY, providing serdes lanes */
Dcn9131-db.dts90 /* Generic PHY, providing serdes lanes */
119 /* Generic PHY, providing serdes lanes */
129 /* Generic PHY, providing serdes lanes */
199 /* Generic PHY, providing serdes lanes */
/Linux-v5.10/drivers/net/ethernet/amd/xgbe/
Dxgbe-phy-v1.c127 #define XGBE_BLWC_PROPERTY "amd,serdes-blwc"
128 #define XGBE_CDR_RATE_PROPERTY "amd,serdes-cdr-rate"
129 #define XGBE_PQ_SKEW_PROPERTY "amd,serdes-pq-skew"
130 #define XGBE_TX_AMP_PROPERTY "amd,serdes-tx-amp"
131 #define XGBE_DFE_CFG_PROPERTY "amd,serdes-dfe-tap-config"
132 #define XGBE_DFE_ENA_PROPERTY "amd,serdes-dfe-tap-enable"
134 /* Default SerDes settings */
208 /* SerDes UEFI configurable settings.
210 * SerDes settings. The values can be supplied as device
358 netif_dbg(pdata, link, pdata->netdev, "SerDes rx/tx not ready (%#hx)\n", in xgbe_phy_complete_ratechange()
[all …]
/Linux-v5.10/Documentation/devicetree/bindings/mfd/
Dti,j721e-system-controller.yaml46 "^serdes-ln-ctrl@[0-9a-f]+$":
49 This is the SERDES lane control mux. It should follow the bindings
71 serdes_ln_ctrl: serdes-ln-ctrl@4080 {
/Linux-v5.10/drivers/infiniband/hw/hfi1/
Dfirmware.c207 /* the number of fabric SerDes on the SBus */
213 /* SBus fabric SerDes addresses, one set per HFI */
219 /* SBus PCIe SerDes addresses, one set per HFI */
235 /* SBus fabric SerDes broadcast addresses, one per HFI */
239 /* SBus PCIe SerDes broadcast addresses, one per HFI */
1126 * Turn off the SBus and fabric serdes spicos.
1129 * + Must be called after fabric serdes broadcast is set up.
1149 /* disable the fabric serdes spicos */ in turn_off_spicos()
1157 * Reset all of the fabric serdes for this HFI in preparation to take the
1160 * To do a reset, we need to write to to the serdes registers. Unfortunately,
[all …]
/Linux-v5.10/drivers/phy/samsung/
DKconfig93 tristate "Exynos5250 Sata SerDes/PHY driver"
102 Enable this to support SATA SerDes/Phy found on Samsung's
103 Exynos5250 based SoCs.This SerDes/Phy supports SATA 1.5 Gb/s,
/Linux-v5.10/drivers/infiniband/hw/qib/
Dqib_sd7220.c35 * This file contains all of the code that is specific to the SerDes
72 * various SerDes registers by IBC.
78 * used for PCIe, or the single SerDes used for IB.
390 * deals with registers and memory within the SerDes itself.
400 /* SERDES MPU reset recorded in D0 */ in qib_sd7220_init()
410 qib_dev_err(dd, "Failed to load IB SERDES image\n"); in qib_sd7220_init()
426 qib_dev_err(dd, "Failed to set IB SERDES early defaults\n"); in qib_sd7220_init()
437 qib_dev_err(dd, "Failed IB SERDES DAC trim\n"); in qib_sd7220_init()
449 qib_dev_err(dd, "Failed to set IB SERDES presets\n"); in qib_sd7220_init()
454 qib_dev_err(dd, "Failed to set IB SERDES TRIMSELF\n"); in qib_sd7220_init()
[all …]
/Linux-v5.10/drivers/net/dsa/b53/
Db53_serdes.c3 * Northstar Plus switch SerDes/SGMII PHY main logic
197 dev_err(dev->dev, "SerDes not initialized, check settings\n"); in b53_serdes_init()
202 "SerDes lane %d, model: %d, rev %c%d (OUI: 0x%08x)\n", in b53_serdes_init()
213 MODULE_DESCRIPTION("B53 Switch SerDes driver");
/Linux-v5.10/drivers/phy/xilinx/
Dphy-zynqmp.c206 * @serdes: serdes base address
217 void __iomem *serdes; member
254 return readl(gtr_dev->serdes + reg); in xpsgtr_read()
259 writel(value, gtr_dev->serdes + reg); in xpsgtr_write()
274 void __iomem *addr = gtr_phy->dev->serdes in xpsgtr_read_phy()
283 void __iomem *addr = gtr_phy->dev->serdes in xpsgtr_write_phy()
292 void __iomem *addr = gtr_phy->dev->serdes in xpsgtr_clr_set_phy()
934 gtr_dev->serdes = devm_platform_ioremap_resource_byname(pdev, "serdes"); in xpsgtr_probe()
935 if (IS_ERR(gtr_dev->serdes)) in xpsgtr_probe()
936 return PTR_ERR(gtr_dev->serdes); in xpsgtr_probe()

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