| /Linux-v6.6/drivers/clk/hisilicon/ |
| D | clkgate-separated.c | 34 struct clkgate_separated *sclk; in clkgate_separated_enable() local
38 sclk = container_of(hw, struct clkgate_separated, hw); in clkgate_separated_enable()
39 if (sclk->lock) in clkgate_separated_enable()
40 spin_lock_irqsave(sclk->lock, flags); in clkgate_separated_enable()
41 reg = BIT(sclk->bit_idx); in clkgate_separated_enable()
42 writel_relaxed(reg, sclk->enable); in clkgate_separated_enable()
43 readl_relaxed(sclk->enable + CLKGATE_SEPERATED_STATUS); in clkgate_separated_enable()
44 if (sclk->lock) in clkgate_separated_enable()
45 spin_unlock_irqrestore(sclk->lock, flags); in clkgate_separated_enable()
51 struct clkgate_separated *sclk; in clkgate_separated_disable() local
[all …]
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| /Linux-v6.6/drivers/clk/meson/ |
| D | sclk-div.c | 23 #include "sclk-div.h"
31 static int sclk_div_maxval(struct meson_sclk_div_data *sclk) in sclk_div_maxval() argument
33 return (1 << sclk->div.width) - 1; in sclk_div_maxval()
36 static int sclk_div_maxdiv(struct meson_sclk_div_data *sclk) in sclk_div_maxdiv() argument
38 return sclk_div_maxval(sclk) + 1; in sclk_div_maxdiv()
51 struct meson_sclk_div_data *sclk) in sclk_div_bestdiv() argument
61 maxdiv = sclk_div_maxdiv(sclk); in sclk_div_bestdiv()
92 bestdiv = sclk_div_maxdiv(sclk); in sclk_div_bestdiv()
103 struct meson_sclk_div_data *sclk = meson_sclk_div_data(clk); in sclk_div_determine_rate() local
106 div = sclk_div_bestdiv(hw, req->rate, &req->best_parent_rate, sclk); in sclk_div_determine_rate()
[all …]
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| /Linux-v6.6/drivers/clk/ralink/ |
| D | clk-mt7621.c | 134 struct mt7621_gate *sclk) in mt7621_gate_ops_init() argument
145 .parent_names = &sclk->parent_name, in mt7621_gate_ops_init()
147 .name = sclk->name, in mt7621_gate_ops_init()
150 sclk->hw.init = &init; in mt7621_gate_ops_init()
151 return devm_clk_hw_register(dev, &sclk->hw); in mt7621_gate_ops_init()
159 struct mt7621_gate *sclk; in mt7621_register_gates() local
163 sclk = &mt7621_gates[i]; in mt7621_register_gates()
164 sclk->priv = priv; in mt7621_register_gates()
165 ret = mt7621_gate_ops_init(dev, sclk); in mt7621_register_gates()
167 dev_err(dev, "Couldn't register clock %s\n", sclk->name); in mt7621_register_gates()
[all …]
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| D | clk-mtmips.c | 231 struct mtmips_clk *sclk; in mtmips_register_pherip_clocks() local
239 sclk = &priv->data->clk_periph[i]; in mtmips_register_pherip_clocks()
240 ret = of_clk_hw_register(np, &sclk->hw); in mtmips_register_pherip_clocks()
246 hws[idx] = &sclk->hw; in mtmips_register_pherip_clocks()
253 sclk = &priv->data->clk_periph[i]; in mtmips_register_pherip_clocks()
254 clk_hw_unregister(&sclk->hw); in mtmips_register_pherip_clocks()
283 struct mtmips_clk_fixed *sclk; in mtmips_register_fixed_clocks() local
290 sclk = &priv->data->clk_fixed[i]; in mtmips_register_fixed_clocks()
291 sclk->hw = clk_hw_register_fixed_rate(NULL, sclk->name, in mtmips_register_fixed_clocks()
292 sclk->parent, 0, in mtmips_register_fixed_clocks()
[all …]
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| /Linux-v6.6/drivers/clk/ |
| D | clk-scmi.c | 134 static int scmi_clk_ops_init(struct device *dev, struct scmi_clk *sclk, in scmi_clk_ops_init() argument
144 .name = sclk->info->name, in scmi_clk_ops_init()
147 sclk->hw.init = &init; in scmi_clk_ops_init()
148 ret = devm_clk_hw_register(dev, &sclk->hw); in scmi_clk_ops_init()
152 if (sclk->info->rate_discrete) { in scmi_clk_ops_init()
153 int num_rates = sclk->info->list.num_rates; in scmi_clk_ops_init()
158 min_rate = sclk->info->list.rates[0]; in scmi_clk_ops_init()
159 max_rate = sclk->info->list.rates[num_rates - 1]; in scmi_clk_ops_init()
161 min_rate = sclk->info->range.min_rate; in scmi_clk_ops_init()
162 max_rate = sclk->info->range.max_rate; in scmi_clk_ops_init()
[all …]
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| D | clk-scpi.c | 139 struct scpi_clk *sclk, const char *name) in scpi_clk_ops_init() argument
149 sclk->hw.init = &init; in scpi_clk_ops_init()
150 sclk->scpi_ops = get_scpi_ops(); in scpi_clk_ops_init()
153 sclk->info = sclk->scpi_ops->dvfs_get_info(sclk->id); in scpi_clk_ops_init()
154 if (IS_ERR(sclk->info)) in scpi_clk_ops_init()
155 return PTR_ERR(sclk->info); in scpi_clk_ops_init()
157 if (sclk->scpi_ops->clk_get_range(sclk->id, &min, &max) || !max) in scpi_clk_ops_init()
163 ret = devm_clk_hw_register(dev, &sclk->hw); in scpi_clk_ops_init()
165 clk_hw_set_rate_range(&sclk->hw, min, max); in scpi_clk_ops_init()
177 struct scpi_clk *sclk; in scpi_of_clk_src_get() local
[all …]
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| D | clk-nomadik.c | 305 struct clk_src *sclk = to_src(hw); in src_clk_enable() local
306 u32 enreg = sclk->group1 ? SRC_PCKEN1 : SRC_PCKEN0; in src_clk_enable()
307 u32 sreg = sclk->group1 ? SRC_PCKSR1 : SRC_PCKSR0; in src_clk_enable()
309 writel(sclk->clkbit, src_base + enreg); in src_clk_enable()
311 while (!(readl(src_base + sreg) & sclk->clkbit)) in src_clk_enable()
318 struct clk_src *sclk = to_src(hw); in src_clk_disable() local
319 u32 disreg = sclk->group1 ? SRC_PCKDIS1 : SRC_PCKDIS0; in src_clk_disable()
320 u32 sreg = sclk->group1 ? SRC_PCKSR1 : SRC_PCKSR0; in src_clk_disable()
322 writel(sclk->clkbit, src_base + disreg); in src_clk_disable()
324 while (readl(src_base + sreg) & sclk->clkbit) in src_clk_disable()
[all …]
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| /Linux-v6.6/drivers/clk/microchip/ |
| D | clk-core.c | 759 /* System mux clock(aka SCLK) */
774 struct pic32_sys_clk *sclk = clkhw_to_sys_clk(hw); in sclk_get_rate() local
777 div = (readl(sclk->slew_reg) >> SLEW_SYSDIV_SHIFT) & SLEW_SYSDIV; in sclk_get_rate()
792 struct pic32_sys_clk *sclk = clkhw_to_sys_clk(hw); in sclk_set_rate() local
799 spin_lock_irqsave(&sclk->core->reg_lock, flags); in sclk_set_rate()
802 v = readl(sclk->slew_reg); in sclk_set_rate()
808 writel(v, sclk->slew_reg); in sclk_set_rate()
811 err = readl_poll_timeout_atomic(sclk->slew_reg, v, in sclk_set_rate()
814 spin_unlock_irqrestore(&sclk->core->reg_lock, flags); in sclk_set_rate()
821 struct pic32_sys_clk *sclk = clkhw_to_sys_clk(hw); in sclk_get_parent() local
[all …]
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| /Linux-v6.6/drivers/gpu/drm/radeon/ |
| D | rv730_dpm.c | 39 RV770_SMC_SCLK_VALUE *sclk) in rv730_populate_sclk_value() argument
106 sclk->sclk_value = cpu_to_be32(engine_clock); in rv730_populate_sclk_value()
107 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl); in rv730_populate_sclk_value()
108 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2); in rv730_populate_sclk_value()
109 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3); in rv730_populate_sclk_value()
110 sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(cg_spll_spread_spectrum); in rv730_populate_sclk_value()
111 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(cg_spll_spread_spectrum_2); in rv730_populate_sclk_value()
302 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl); in rv730_populate_smc_acpi_state()
303 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2); in rv730_populate_smc_acpi_state()
304 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3); in rv730_populate_smc_acpi_state()
[all …]
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| D | rv770_dpm.c | 273 a_n = (int)state->medium.sclk * pi->lmp + in rv770_populate_smc_t()
274 (int)state->low.sclk * (R600_AH_DFLT - pi->rlp); in rv770_populate_smc_t()
275 a_d = (int)state->low.sclk * (100 - (int)pi->rlp) + in rv770_populate_smc_t()
276 (int)state->medium.sclk * pi->lmp; in rv770_populate_smc_t()
281 a_n = (int)state->high.sclk * pi->lhp + (int)state->medium.sclk * in rv770_populate_smc_t()
283 a_d = (int)state->medium.sclk * (100 - (int)pi->rmp) + in rv770_populate_smc_t()
284 (int)state->high.sclk * pi->lhp; in rv770_populate_smc_t()
487 RV770_SMC_SCLK_VALUE *sclk) in rv770_populate_sclk_value() argument
557 sclk->sclk_value = cpu_to_be32(engine_clock); in rv770_populate_sclk_value()
558 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl); in rv770_populate_sclk_value()
[all …]
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| D | trinity_dpm.c | 540 u32 index, u32 sclk) in trinity_set_divider_value() argument
548 sclk, false, ÷rs); in trinity_set_divider_value()
558 sclk/2, false, ÷rs); in trinity_set_divider_value()
678 trinity_set_divider_value(rdev, index, pl->sclk); in trinity_program_power_level()
925 if (new_ps->levels[new_ps->num_levels - 1].sclk >= in trinity_set_uvd_clock_before_set_eng_clock()
926 current_ps->levels[current_ps->num_levels - 1].sclk) in trinity_set_uvd_clock_before_set_eng_clock()
939 if (new_ps->levels[new_ps->num_levels - 1].sclk < in trinity_set_uvd_clock_after_set_eng_clock()
940 current_ps->levels[current_ps->num_levels - 1].sclk) in trinity_set_uvd_clock_after_set_eng_clock()
1290 static u8 trinity_calculate_vce_wm(struct radeon_device *rdev, u32 sclk) in trinity_calculate_vce_wm() argument
1292 if (sclk < 20000) in trinity_calculate_vce_wm()
[all …]
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| D | sumo_dpm.c | 347 u32 highest_engine_clock = ps->levels[ps->num_levels - 1].sclk; in sumo_program_bsp()
350 highest_engine_clock = pi->boost_pl.sclk; in sumo_program_bsp()
411 m_a = asi * ps->levels[i].sclk / 100; in sumo_program_at()
421 m_a = asi * pi->boost_pl.sclk / 100; in sumo_program_at()
555 pl->sclk, false, ÷rs); in sumo_program_power_level()
671 pi->boost_pl.sclk = pi->sys_info.boost_sclk; in sumo_patch_boost_state()
790 pi->acpi_pl.sclk, in sumo_program_acpi_power_level()
844 if (new_ps->levels[new_ps->num_levels - 1].sclk >= in sumo_set_uvd_clock_before_set_eng_clock()
845 current_ps->levels[current_ps->num_levels - 1].sclk) in sumo_set_uvd_clock_before_set_eng_clock()
862 if (new_ps->levels[new_ps->num_levels - 1].sclk < in sumo_set_uvd_clock_after_set_eng_clock()
[all …]
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| D | btc_dpm.c | 1242 u32 *sclk, u32 *mclk) in btc_skip_blacklist_clocks() argument
1246 if ((sclk == NULL) || (mclk == NULL)) in btc_skip_blacklist_clocks()
1252 if ((btc_blacklist_clocks[i].sclk == *sclk) && in btc_skip_blacklist_clocks()
1259 *sclk = btc_get_valid_sclk(rdev, max_sclk, *sclk + 1); in btc_skip_blacklist_clocks()
1261 if (*sclk < max_sclk) in btc_skip_blacklist_clocks()
1262 btc_skip_blacklist_clocks(rdev, max_sclk, max_mclk, sclk, mclk); in btc_skip_blacklist_clocks()
1272 if ((pl->mclk == 0) || (pl->sclk == 0)) in btc_adjust_clock_combinations()
1275 if (pl->mclk == pl->sclk) in btc_adjust_clock_combinations()
1278 if (pl->mclk > pl->sclk) { in btc_adjust_clock_combinations()
1279 if (((pl->mclk + (pl->sclk - 1)) / pl->sclk) > rdev->pm.dpm.dyn_state.mclk_sclk_ratio) in btc_adjust_clock_combinations()
[all …]
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| D | rv740_dpm.c | 120 RV770_SMC_SCLK_VALUE *sclk) in rv740_populate_sclk_value() argument
175 sclk->sclk_value = cpu_to_be32(engine_clock); in rv740_populate_sclk_value()
176 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl); in rv740_populate_sclk_value()
177 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2); in rv740_populate_sclk_value()
178 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3); in rv740_populate_sclk_value()
179 sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(cg_spll_spread_spectrum); in rv740_populate_sclk_value()
180 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(cg_spll_spread_spectrum_2); in rv740_populate_sclk_value()
385 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl); in rv740_populate_smc_acpi_state()
386 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2); in rv740_populate_smc_acpi_state()
387 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3); in rv740_populate_smc_acpi_state()
[all …]
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| D | kv_dpm.c | 377 u32 index, u32 sclk) in kv_set_divider_value() argument
384 sclk, false, ÷rs); in kv_set_divider_value()
389 pi->graphics_level[index].SclkFrequency = cpu_to_be32(sclk); in kv_set_divider_value()
566 if (table->entries[i].clk == pi->boot_pl.sclk) in kv_program_bootup_state()
580 if (table->entries[i].sclk_frequency == pi->boot_pl.sclk) in kv_program_bootup_state()
1537 if ((table->entries[i].clk >= new_ps->levels[0].sclk) || in kv_set_valid_clock_range()
1545 if (table->entries[i].clk <= new_ps->levels[new_ps->num_levels - 1].sclk) in kv_set_valid_clock_range()
1551 if ((new_ps->levels[0].sclk - table->entries[pi->highest_valid].clk) > in kv_set_valid_clock_range()
1552 (table->entries[pi->lowest_valid].clk - new_ps->levels[new_ps->num_levels - 1].sclk)) in kv_set_valid_clock_range()
1562 if (table->entries[i].sclk_frequency >= new_ps->levels[0].sclk || in kv_set_valid_clock_range()
[all …]
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| /Linux-v6.6/drivers/gpu/drm/nouveau/nvkm/subdev/clk/ |
| D | gk104.c | 68 u32 sclk; in read_pll() local
77 sclk = device->crystal; in read_pll()
81 sclk = read_pll(clk, 0x132020); in read_pll()
85 sclk = read_div(clk, 0, 0x137320, 0x137330); in read_pll()
92 sclk = read_div(clk, (pll & 0xff) / 0x20, 0x137120, 0x137140); in read_pll()
101 sclk = (sclk * N) + (((u16)(fN + 4096) * sclk) >> 13); in read_pll()
102 return sclk / (M * P); in read_pll()
121 u32 sclk = read_vco(clk, dsrc + (doff * 4)); in read_div() local
123 return (sclk * 2) / sdiv; in read_div()
149 u32 sclk, sdiv; in read_clk() local
[all …]
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| D | gf100.c | 67 u32 sclk; in read_pll() local
75 sclk = device->crystal; in read_pll()
79 sclk = nvkm_clk_read(&clk->base, nv_clk_src_mpllsrc); in read_pll()
82 sclk = nvkm_clk_read(&clk->base, nv_clk_src_mpllsrcref); in read_pll()
88 sclk = read_div(clk, (pll & 0xff) / 0x20, 0x137120, 0x137140); in read_pll()
94 return sclk * N / M / P; in read_pll()
102 u32 sclk, sctl, sdiv = 2; in read_div() local
112 sclk = read_vco(clk, dsrc + (doff * 4)); in read_div()
126 return (sclk * 2) / sdiv; in read_div()
138 u32 sclk, sdiv; in read_clk() local
[all …]
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| /Linux-v6.6/sound/soc/intel/skylake/ |
| D | skl-nhlt.c | 90 * sclk/sclkfs.
98 struct skl_ssp_clk *sclk, *sclkfs; in skl_get_ssp_clks() local
108 sclk = &ssp_clks[SKL_SCLK_OFS]; in skl_get_ssp_clks()
129 * But the sclk rate will be generated for the total in skl_get_ssp_clks()
153 /* check if the rate is added already to the given SSP's sclk */ in skl_get_ssp_clks()
155 (sclk[id].rate_cfg[j].rate != 0); j++) { in skl_get_ssp_clks()
156 if (sclk[id].rate_cfg[j].rate == rate) { in skl_get_ssp_clks()
162 /* Fill rate and parent for sclk/sclkfs */ in skl_get_ssp_clks()
192 sclk[id].rate_cfg[rate_index].rate = rate; in skl_get_ssp_clks()
193 sclk[id].rate_cfg[rate_index].config = saved_fmt_cfg; in skl_get_ssp_clks()
[all …]
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| /Linux-v6.6/sound/soc/cirrus/ |
| D | ep93xx-i2s.c | 76 struct clk *sclk; member
116 clk_prepare_enable(info->sclk); in ep93xx_i2s_enable()
161 clk_disable_unprepare(info->sclk); in ep93xx_i2s_disable()
337 * EP93xx I2S module can be setup so SCLK / LRCLK value can be in ep93xx_i2s_hw_params()
338 * 32, 64, 128. MCLK / SCLK value can be 2 and 4. in ep93xx_i2s_hw_params()
339 * We set LRCLK equal to `rate' and minimum SCLK / LRCLK in ep93xx_i2s_hw_params()
354 err = clk_set_rate(info->sclk, clk_get_rate(info->mclk) / sdiv); in ep93xx_i2s_hw_params()
358 err = clk_set_rate(info->lrclk, clk_get_rate(info->sclk) / lrdiv); in ep93xx_i2s_hw_params()
474 info->sclk = clk_get(&pdev->dev, "sclk"); in ep93xx_i2s_probe()
475 if (IS_ERR(info->sclk)) { in ep93xx_i2s_probe()
[all …]
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| /Linux-v6.6/sound/soc/meson/ |
| D | axg-tdm-formatter.c | 20 struct clk *sclk; member
109 * If sclk is inverted, it means the bit should latched on the in axg_tdm_formatter_enable()
114 ret = clk_set_phase(formatter->sclk, invert ? 0 : 180); in axg_tdm_formatter_enable()
126 ret = clk_prepare_enable(formatter->sclk); in axg_tdm_formatter_enable()
132 clk_disable_unprepare(formatter->sclk); in axg_tdm_formatter_enable()
151 clk_disable_unprepare(formatter->sclk); in axg_tdm_formatter_disable()
208 ret = clk_set_parent(formatter->sclk_sel, ts->iface->sclk); in axg_tdm_formatter_power_up()
298 formatter->sclk = devm_clk_get(dev, "sclk"); in axg_tdm_formatter_probe()
299 if (IS_ERR(formatter->sclk)) in axg_tdm_formatter_probe()
300 return dev_err_probe(dev, PTR_ERR(formatter->sclk), "failed to get sclk\n"); in axg_tdm_formatter_probe()
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| /Linux-v6.6/Documentation/devicetree/bindings/clock/ |
| D | nvidia,tegra20-car.yaml | 46 "^(sclk)|(pll-[cem])$":
51 - nvidia,tegra20-sclk
52 - nvidia,tegra30-sclk
93 sclk {
94 compatible = "nvidia,tegra20-sclk";
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| /Linux-v6.6/drivers/gpu/drm/armada/ |
| D | armada_510.c | 95 * Armada510 specific SCLK register selection.
96 * This gets called with sclk = NULL to test whether the mode is
97 * supportable, and again with sclk != NULL to set the clocks up for
102 const struct drm_display_mode *mode, uint32_t *sclk) in armada510_crtc_compute_clock() argument
119 if (sclk) { in armada510_crtc_compute_clock()
122 *sclk = res.div | armada510_clk_sels[idx]; in armada510_crtc_compute_clock()
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| /Linux-v6.6/drivers/gpu/drm/amd/pm/swsmu/smu11/ |
| D | cyan_skillfish_ppt.c | 57 uint32_t sclk; member
317 size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n", in cyan_skillfish_print_clk_levels()
374 * cyan_skillfish specific, query default sclk inseted of hard code. in cyan_skillfish_is_dpm_running()
454 dev_err(smu->adev->dev, "Invalid sclk! Valid sclk range: %uMHz - %uMhz\n", in cyan_skillfish_od_edit_dpm_table()
466 cyan_skillfish_user_settings.sclk = input[1]; in cyan_skillfish_od_edit_dpm_table()
476 cyan_skillfish_user_settings.sclk = cyan_skillfish_sclk_default; in cyan_skillfish_od_edit_dpm_table()
486 if (cyan_skillfish_user_settings.sclk < CYAN_SKILLFISH_SCLK_MIN || in cyan_skillfish_od_edit_dpm_table()
487 cyan_skillfish_user_settings.sclk > CYAN_SKILLFISH_SCLK_MAX) { in cyan_skillfish_od_edit_dpm_table()
488 dev_err(smu->adev->dev, "Invalid sclk! Valid sclk range: %uMHz - %uMhz\n", in cyan_skillfish_od_edit_dpm_table()
502 cyan_skillfish_user_settings.sclk, NULL); in cyan_skillfish_od_edit_dpm_table()
[all …]
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| /Linux-v6.6/drivers/power/reset/ |
| D | at91-poweroff.c | 55 struct clk *sclk; member
162 at91_shdwc.sclk = devm_clk_get(&pdev->dev, NULL); in at91_poweroff_probe()
163 if (IS_ERR(at91_shdwc.sclk)) in at91_poweroff_probe()
164 return PTR_ERR(at91_shdwc.sclk); in at91_poweroff_probe()
166 ret = clk_prepare_enable(at91_shdwc.sclk); in at91_poweroff_probe()
201 clk_disable_unprepare(at91_shdwc.sclk); in at91_poweroff_probe()
213 clk_disable_unprepare(at91_shdwc.sclk); in at91_poweroff_remove()
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| /Linux-v6.6/arch/arm64/boot/dts/amlogic/ |
| D | meson-g12.dtsi | 21 clock-names = "mclk", "sclk", "lrclk";
32 clock-names = "mclk", "sclk", "lrclk";
43 clock-names = "mclk", "sclk", "lrclk";
208 clock-names = "pclk", "sclk", "sclk_sel",
224 clock-names = "pclk", "sclk", "sclk_sel",
240 clock-names = "pclk", "sclk", "sclk_sel",
256 clock-names = "pclk", "sclk", "sclk_sel",
298 clock-names = "pclk", "sclk", "sclk_sel",
313 clock-names = "pclk", "sclk", "sclk_sel",
328 clock-names = "pclk", "sclk", "sclk_sel",
|
