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/Linux-v5.10/arch/arm/boot/dts/
Dimx7ulp.dtsi132 <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>;
155 assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
167 assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
176 assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
186 clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
222 clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
223 <&scg1 IMX7ULP_CLK_NIC1_DIV>,
236 clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
237 <&scg1 IMX7ULP_CLK_NIC1_DIV>,
246 scg1: clock-controller@403e0000 { label
[all …]
Dimx7ulp-com.dts41 assigned-clock-parents = <&scg1 IMX7ULP_CLK_APLL_PFD1>;
Dimx7ulp-evk.dts81 assigned-clock-parents = <&scg1 IMX7ULP_CLK_APLL_PFD1>;
/Linux-v5.10/Documentation/devicetree/bindings/clock/
Dimx7ulp-pcc-clock.yaml24 A7 clock management consists of SCG1, PCC2, PCC3, and CMC1 modules.
95 clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
96 <&scg1 IMX7ULP_CLK_NIC1_DIV>,
97 <&scg1 IMX7ULP_CLK_DDR_DIV>,
98 <&scg1 IMX7ULP_CLK_APLL_PFD2>,
99 <&scg1 IMX7ULP_CLK_APLL_PFD1>,
100 <&scg1 IMX7ULP_CLK_APLL_PFD0>,
101 <&scg1 IMX7ULP_CLK_UPLL>,
102 <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>,
103 <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>,
[all …]
Dimx7ulp-scg-clock.yaml24 A7 clock management consists of SCG1, PCC2, PCC3, and CMC1 modules.
42 const: fsl,imx7ulp-scg1
81 compatible = "fsl,imx7ulp-scg1";
94 clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
95 <&scg1 IMX7ULP_CLK_NIC1_DIV>,
/Linux-v5.10/Documentation/devicetree/bindings/pwm/
Dimx-tpm-pwm.yaml52 assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
/Linux-v5.10/Documentation/devicetree/bindings/watchdog/
Dfsl-imx7ulp-wdt.yaml56 assigned-clocks-parents = <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>;
/Linux-v5.10/Documentation/devicetree/bindings/timer/
Dnxp,tpm-timer.yaml58 clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
/Linux-v5.10/include/dt-bindings/clock/
Dimx7ulp-clock.h11 /* SCG1 */
/Linux-v5.10/drivers/clk/imx/
Dclk-imx7ulp.c81 /* SCG1 */ in imx7ulp_clk_scg1_init()
146 CLK_OF_DECLARE(imx7ulp_clk_scg1, "fsl,imx7ulp-scg1", imx7ulp_clk_scg1_init);