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/Linux-v6.1/drivers/net/wireless/realtek/rtw88/
Dsar.c5 #include "sar.h"
12 const struct rtw_sar *sar = &hal->sar; in rtw_query_sar() local
14 switch (sar->src) { in rtw_query_sar()
16 rtw_warn(rtwdev, "unknown SAR source: %d\n", sar->src); in rtw_query_sar()
21 return sar->cfg[arg->path][arg->rs].common[arg->sar_band]; in rtw_query_sar()
28 struct rtw_sar *sar = &hal->sar; in rtw_apply_sar() local
30 if (sar->src != RTW_SAR_SOURCE_NONE && new->src != sar->src) { in rtw_apply_sar()
31 rtw_warn(rtwdev, "SAR source: %d is in use\n", sar->src); in rtw_apply_sar()
35 *sar = *new; in rtw_apply_sar()
41 static s8 rtw_sar_to_phy(struct rtw_dev *rtwdev, u8 fct, s32 sar, in rtw_sar_to_phy() argument
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/Linux-v6.1/Documentation/devicetree/bindings/sound/
Dnau8824.txt29 - nuvoton,sar-threshold-num: Number of buttons supported
30 …- nuvoton,sar-threshold: Impedance threshold for each button. Array that contains up to 8 buttons …
31 SAR = 255 * MICBIAS / SAR_VOLTAGE * R / (2000 + R)
32 …igured by 'nuvoton,micbias-voltage', SAR_VOLTAGE is configured by 'nuvoton,sar-voltage', R - butto…
35 - nuvoton,sar-hysteresis: Button impedance measurement hysteresis.
37 - nuvoton,sar-voltage: Reference voltage for button impedance measurement.
47 - nuvoton,sar-compare-time: SAR compare time
53 - nuvoton,sar-sampling-time: SAR sampling time
80 nuvoton,sar-threshold-num = <4>;
81 nuvoton,sar-threshold = <0xc 0x1e 0x38 0x60>;
[all …]
Dnau8825.txt33 - nuvoton,sar-threshold-num: Number of buttons supported
34 …- nuvoton,sar-threshold: Impedance threshold for each button. Array that contains up to 8 buttons …
35 SAR = 255 * MICBIAS / SAR_VOLTAGE * R / (2000 + R)
36 …igured by 'nuvoton,micbias-voltage', SAR_VOLTAGE is configured by 'nuvoton,sar-voltage', R - butto…
39 - nuvoton,sar-hysteresis: Button impedance measurement hysteresis.
41 - nuvoton,sar-voltage: Reference voltage for button impedance measurement.
51 - nuvoton,sar-compare-time: SAR compare time
57 - nuvoton,sar-sampling-time: SAR sampling time
95 nuvoton,sar-threshold-num = <4>;
96 nuvoton,sar-threshold = <0xc 0x1e 0x38 0x60>;
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/Linux-v6.1/drivers/clk/mvebu/
Dorion.c28 static u32 __init mv88f5181_get_tclk_freq(void __iomem *sar) in mv88f5181_get_tclk_freq() argument
30 u32 opt = (readl(sar) >> SAR_MV88F5181_TCLK_FREQ) & in mv88f5181_get_tclk_freq()
45 static u32 __init mv88f5181_get_cpu_freq(void __iomem *sar) in mv88f5181_get_cpu_freq() argument
47 u32 opt = (readl(sar) >> SAR_MV88F5181_CPU_FREQ) & in mv88f5181_get_cpu_freq()
59 static void __init mv88f5181_get_clk_ratio(void __iomem *sar, int id, in mv88f5181_get_clk_ratio() argument
62 u32 opt = (readl(sar) >> SAR_MV88F5181_CPU_FREQ) & in mv88f5181_get_clk_ratio()
98 static u32 __init mv88f5182_get_tclk_freq(void __iomem *sar) in mv88f5182_get_tclk_freq() argument
100 u32 opt = (readl(sar) >> SAR_MV88F5182_TCLK_FREQ) & in mv88f5182_get_tclk_freq()
113 static u32 __init mv88f5182_get_cpu_freq(void __iomem *sar) in mv88f5182_get_cpu_freq() argument
115 u32 opt = (readl(sar) >> SAR_MV88F5182_CPU_FREQ) & in mv88f5182_get_cpu_freq()
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Dkirkwood.c25 * (6180 has different SAR layout than other Kirkwood SoCs)
86 static u32 __init kirkwood_get_tclk_freq(void __iomem *sar) in kirkwood_get_tclk_freq() argument
88 u32 opt = (readl(sar) >> SAR_KIRKWOOD_TCLK_FREQ) & in kirkwood_get_tclk_freq()
108 static u32 __init kirkwood_get_cpu_freq(void __iomem *sar) in kirkwood_get_cpu_freq() argument
110 u32 opt = SAR_KIRKWOOD_CPU_FREQ(readl(sar)); in kirkwood_get_cpu_freq()
127 void __iomem *sar, int id, int *mult, int *div) in kirkwood_get_clk_ratio() argument
132 u32 opt = SAR_KIRKWOOD_L2_RATIO(readl(sar)); in kirkwood_get_clk_ratio()
139 u32 opt = (readl(sar) >> SAR_KIRKWOOD_DDR_RATIO) & in kirkwood_get_clk_ratio()
155 static u32 __init mv88f6180_get_cpu_freq(void __iomem *sar) in mv88f6180_get_cpu_freq() argument
157 u32 opt = (readl(sar) >> SAR_MV88F6180_CLK) & SAR_MV88F6180_CLK_MASK; in mv88f6180_get_cpu_freq()
[all …]
Dcommon.h28 u32 (*get_tclk_freq)(void __iomem *sar);
29 u32 (*get_cpu_freq)(void __iomem *sar);
30 void (*get_clk_ratio)(void __iomem *sar, int id, int *mult, int *div);
31 u32 (*get_refclk_freq)(void __iomem *sar);
32 bool (*is_sscg_enabled)(void __iomem *sar);
Darmada-39x.c45 static u32 __init armada_39x_get_tclk_freq(void __iomem *sar) in armada_39x_get_tclk_freq() argument
49 tclk_freq_select = ((readl(sar + SARL) >> SARL_A390_TCLK_FREQ_OPT) & in armada_39x_get_tclk_freq()
68 static u32 __init armada_39x_get_cpu_freq(void __iomem *sar) in armada_39x_get_cpu_freq() argument
72 cpu_freq_select = ((readl(sar + SARL) >> SARL_A390_CPU_DDR_L2_FREQ_OPT) & in armada_39x_get_cpu_freq()
92 void __iomem *sar, int id, int *mult, int *div) in armada_39x_get_clk_ratio() argument
110 static u32 __init armada_39x_refclk_ratio(void __iomem *sar) in armada_39x_refclk_ratio() argument
112 if (readl(sar + SARH) & SARH_A390_REFCLK_FREQ) in armada_39x_refclk_ratio()
Darmada-38x.c20 * SAR[14:10] : Ratios between PCLK0, NBCLK, HCLK and DRAM clocks
22 * SAR[15] : TCLK frequency
37 static u32 __init armada_38x_get_tclk_freq(void __iomem *sar) in armada_38x_get_tclk_freq() argument
41 tclk_freq_select = ((readl(sar) >> SAR_A380_TCLK_FREQ_OPT) & in armada_38x_get_tclk_freq()
54 static u32 __init armada_38x_get_cpu_freq(void __iomem *sar) in armada_38x_get_cpu_freq() argument
58 cpu_freq_select = ((readl(sar) >> SAR_A380_CPU_DDR_L2_FREQ_OPT) & in armada_38x_get_cpu_freq()
99 void __iomem *sar, int id, int *mult, int *div) in armada_38x_get_clk_ratio() argument
101 u32 opt = ((readl(sar) >> SAR_A380_CPU_DDR_L2_FREQ_OPT) & in armada_38x_get_clk_ratio()
Darmada-370.c45 static u32 __init a370_get_tclk_freq(void __iomem *sar) in a370_get_tclk_freq() argument
49 tclk_freq_select = ((readl(sar) >> SARL_A370_TCLK_FREQ_OPT) & in a370_get_tclk_freq()
64 static u32 __init a370_get_cpu_freq(void __iomem *sar) in a370_get_cpu_freq() argument
69 cpu_freq_select = ((readl(sar) >> SARL_A370_PCLK_FREQ_OPT) & in a370_get_cpu_freq()
114 void __iomem *sar, int id, int *mult, int *div) in a370_get_clk_ratio() argument
116 u32 opt = ((readl(sar) >> SARL_A370_FAB_FREQ_OPT) & in a370_get_clk_ratio()
135 static bool a370_is_sscg_enabled(void __iomem *sar) in a370_is_sscg_enabled() argument
137 return !(readl(sar) & SARL_A370_SSCG_ENABLE); in a370_is_sscg_enabled()
Darmada-xp.c48 static u32 __init axp_get_tclk_freq(void __iomem *sar) in axp_get_tclk_freq() argument
68 static u32 __init axp_get_cpu_freq(void __iomem *sar) in axp_get_cpu_freq() argument
73 cpu_freq_select = ((readl(sar + SARL) >> SARL_AXP_PCLK_FREQ_OPT) & in axp_get_cpu_freq()
77 * located in the high part of the SAR registers in axp_get_cpu_freq()
79 cpu_freq_select |= (((readl(sar + SARH) >> SARH_AXP_PCLK_FREQ_OPT) & in axp_get_cpu_freq()
124 void __iomem *sar, int id, int *mult, int *div) in axp_get_clk_ratio() argument
126 u32 opt = ((readl(sar + SARL) >> SARL_AXP_FAB_FREQ_OPT) & in axp_get_clk_ratio()
130 * located in the high part of the SAR registers in axp_get_clk_ratio()
132 opt |= (((readl(sar + SARH) >> SARH_AXP_FAB_FREQ_OPT) & in axp_get_clk_ratio()
Ddove.c87 static u32 __init dove_get_tclk_freq(void __iomem *sar) in dove_get_tclk_freq() argument
89 u32 opt = (readl(sar) >> SAR_DOVE_TCLK_FREQ) & in dove_get_tclk_freq()
106 static u32 __init dove_get_cpu_freq(void __iomem *sar) in dove_get_cpu_freq() argument
108 u32 opt = (readl(sar) >> SAR_DOVE_CPU_FREQ) & in dove_get_cpu_freq()
126 void __iomem *sar, int id, int *mult, int *div) in dove_get_clk_ratio() argument
131 u32 opt = (readl(sar) >> SAR_DOVE_L2_RATIO) & in dove_get_clk_ratio()
139 u32 opt = (readl(sar) >> SAR_DOVE_DDR_RATIO) & in dove_get_clk_ratio()
Dmv98dx3236.c44 static u32 __init mv98dx3236_get_tclk_freq(void __iomem *sar) in mv98dx3236_get_tclk_freq() argument
46 /* Tclk = 200MHz, no SaR dependency */ in mv98dx3236_get_tclk_freq()
68 static u32 __init mv98dx3236_get_cpu_freq(void __iomem *sar) in mv98dx3236_get_cpu_freq() argument
73 cpu_freq_select = ((readl(sar) >> SAR1_MV98DX3236_CPU_DDR_MPLL_FREQ_OPT) & in mv98dx3236_get_cpu_freq()
118 void __iomem *sar, int id, int *mult, int *div) in mv98dx3236_get_clk_ratio() argument
120 u32 opt = ((readl(sar) >> SAR1_MV98DX3236_CPU_DDR_MPLL_FREQ_OPT) & in mv98dx3236_get_clk_ratio()
Darmada-375.c50 static u32 __init armada_375_get_tclk_freq(void __iomem *sar) in armada_375_get_tclk_freq() argument
54 tclk_freq_select = ((readl(sar) >> SAR1_A375_TCLK_FREQ_OPT) & in armada_375_get_tclk_freq()
71 static u32 __init armada_375_get_cpu_freq(void __iomem *sar) in armada_375_get_cpu_freq() argument
75 cpu_freq_select = ((readl(sar) >> SAR1_A375_CPU_DDR_L2_FREQ_OPT) & in armada_375_get_cpu_freq()
115 void __iomem *sar, int id, int *mult, int *div) in armada_375_get_clk_ratio() argument
117 u32 opt = ((readl(sar) >> SAR1_A375_CPU_DDR_L2_FREQ_OPT) & in armada_375_get_clk_ratio()
/Linux-v6.1/drivers/net/wireless/realtek/rtw89/
Dsar.c6 #include "sar.h"
14 "center freq: %u to SAR subband is unhandled\n", in rtw89_sar_get_subband()
63 /* Since 6GHz SAR subbands are not edge aligned, some cases span two SAR
83 struct rtw89_sar_cfg_common *rtwsar = &rtwdev->sar.cfg_common; in rtw89_query_sar_config_common()
111 "for {band %u, center_freq %u}, SAR subband: {%u, %u}\n", in rtw89_query_sar_config_common()
143 _d->sar._cfg_name = *(_cfg_data); \
144 _d->sar.src = _s; \
162 const enum rtw89_sar_sources src = rtwdev->sar.src; in rtw89_query_sar()
185 const enum rtw89_sar_sources src = rtwdev->sar.src; in rtw89_print_sar()
196 seq_puts(m, "no SAR is applied\n"); in rtw89_print_sar()
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/Linux-v6.1/Documentation/ABI/testing/
Dsysfs-driver-intc_sar7 Specific Absorption Rate (SAR) regulatory mode is typically
11 the current SAR regulatory mode on the Dynamic SAR driver using
14 from the Dynamic SAR driver.
32 This sysfs entry is used to retrieve Dynamic SAR information
33 emitted/maintained by a BIOS that supports Dynamic SAR.
44 level using the Band/Antenna/SAR table index information.
48 given host. The regulatory mode configured on Dynamic SAR
/Linux-v6.1/drivers/platform/x86/intel/int1092/
DKconfig7 M.2 modem to regulate the RF power based on SAR data obtained from the
9 to SAR driver. The front end application in userspace will interact with SAR
11 SAR table index and use available communication like MBIM interface to enable
13 given platform needs to support "Dynamic SAR" configuration for a modem available
Dintel_sar.h25 * @sartable_index: Index of SAR
54 * @bios_table_revision: Version of SAR table
64 * Structure wwan_sar_context - context of SAR
/Linux-v6.1/arch/parisc/kernel/
Dperf_asm.S154 shrpd ret0,%r0,%sar,%r1
178 shrpd ret0,%r0,%sar,%r1
274 shrpd ret0,%r0,%sar,%r1
286 shrpd ret0,%r0,%sar,%r1
322 shrpd ret0,%r0,%sar,%r1
358 shrpd ret0,%r0,%sar,%r1
370 shrpd ret0,%r0,%sar,%r1
466 shrpd ret0,%r0,%sar,%r1
478 shrpd ret0,%r0,%sar,%r1
514 shrpd ret0,%r0,%sar,%r1
[all …]
Dsignal32.c98 /* Load the upper half for sar */ in restore_sigcontext32()
100 regs->sar = ((u64)compat_regt << 32) | (u64)compat_reg; in restore_sigcontext32()
101 DBG(2,"restore_sigcontext32: upper_half & sar = %#lx\n", compat_regt); in restore_sigcontext32()
102 DBG(2,"restore_sigcontext32: sar is %#lx\n", regs->sar); in restore_sigcontext32()
238 compat_reg = (compat_uint_t)(regs->sar); in setup_sigcontext32()
240 DBG(2,"setup_sigcontext32: sar is %#x\n", compat_reg); in setup_sigcontext32()
242 compat_reg = (compat_uint_t)(regs->sar >> 32); in setup_sigcontext32()
244 DBG(2,"setup_sigcontext32: upper half sar = %#x\n", compat_reg); in setup_sigcontext32()
/Linux-v6.1/arch/sh/drivers/dma/
Ddma-g2.c97 if (chan->sar & 31) { in g2_xfer_dma()
98 printk("g2dma: unaligned source 0x%lx\n", chan->sar); in g2_xfer_dma()
117 flush_icache_range((unsigned long)chan->sar, chan->count); in g2_xfer_dma()
122 g2_dma->channel[chan_nr].root_addr = chan->sar & 0x1fffffe0; in g2_xfer_dma()
136 pr_debug("count, sar, dar, mode, ctrl, chan, xfer: %ld, 0x%08lx, " in g2_xfer_dma()
/Linux-v6.1/arch/arm/mach-omap2/
Domap4-sar-layout.h3 * omap4-sar-layout.h: OMAP4 SAR RAM layout header file
12 * SAR BANK offsets from base address OMAP44XX/54XX_SAR_RAM_BASE
/Linux-v6.1/arch/xtensa/kernel/
Dcoprocessor.S152 /* Save remaining registers a1-a3 and SAR */
155 rsr a3, sar
177 /* Set corresponding CPENABLE bit -> (sar:cp-index, a3: 1<<cp-index)*/
179 ssl a3 # SAR: 32 - coprocessor_number
261 wsr a0, sar
/Linux-v6.1/drivers/net/wireless/ath/ath9k/
DKconfig88 TX99 support enables Specific Absorption Rate (SAR) testing.
89 SAR is the unit of measurement for the amount of radio frequency(RF)
91 limits used are expressed in the terms of SAR, which is a measure
96 governmental SAR regulations.
/Linux-v6.1/Documentation/devicetree/bindings/input/
Diqs62x-keys.yaml72 | 10 | SAR Active*** | x | | x | | |
74 | 11 | SAR Quick Rel.*** | x | | x | | |
76 | 12 | SAR Movement*** | x | | x | | |
78 | 13 | SAR Filter Halt*** | x | | x | | |
84 * Two-channel SAR. Replaces CH0-2 plus metal touch and proximity events
88 *** One-channel SAR. Replaces CH0-2 touch and proximity events if enabled
/Linux-v6.1/drivers/net/wireless/mediatek/mt76/mt7921/
Dacpi_sar.c34 dev_err(mdev->dev, "sar cnt = %d\n", in mt7921_acpi_read()
72 /* MTDS : Dynamic SAR Power Table */
107 /* MTGS : Geo SAR Power Table */
266 /* When ACPI SAR enabled in HW, we should apply rules for .frp in mt7921_init_acpi_sar_power()
267 * 1. w/o .sar_specs : set ACPI SAR power as the defatul value in mt7921_init_acpi_sar_power()

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