| /Linux-v6.6/Documentation/driver-api/ |
| D | reset.rst | 4 Reset controller API
10 Reset controllers are central units that control the reset signals to multiple
12 The reset controller API is split into two parts:
14 <#reset-consumer-api>`__), which allows peripheral drivers to request control
15 over their reset input signals, and the `reset controller driver interface
16 <#reset-controller-driver-interface>`__ (`API reference
17 <#reset-controller-driver-api>`__), which is used by drivers for reset
18 controller devices to register their reset controls to provide them to the
21 While some reset controller hardware units also implement system restart
22 functionality, restart handlers are out of scope for the reset controller API.
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| /Linux-v6.6/Documentation/devicetree/bindings/reset/ |
| D | zynq-reset.txt | 1 Xilinx Zynq Reset Manager
8 - compatible: "xlnx,zynq-reset"
12 - #reset-cells: Must be 1
14 The Zynq Reset Manager needs to be a childnode of the SLCR.
18 compatible = "xlnx,zynq-reset";
20 #reset-cells = <1>;
24 Reset outputs:
25 0 : soft reset
26 32 : ddr reset
27 64 : topsw reset
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| D | socionext,uniphier-reset.yaml | 4 $id: http://devicetree.org/schemas/reset/socionext,uniphier-reset.yaml#
7 title: UniPhier reset controller
15 - description: System reset
17 - socionext,uniphier-ld4-reset
18 - socionext,uniphier-pro4-reset
19 - socionext,uniphier-sld8-reset
20 - socionext,uniphier-pro5-reset
21 - socionext,uniphier-pxs2-reset
22 - socionext,uniphier-ld6b-reset
23 - socionext,uniphier-ld11-reset
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| D | reset.txt | 1 = Reset Signal Device Tree Bindings =
3 This binding is intended to represent the hardware reset signals present
4 internally in most IC (SoC, FPGA, ...) designs. Reset signals for whole
8 Hardware blocks typically receive a reset signal. This signal is generated by
9 a reset provider (e.g. power management or clock module) and received by a
10 reset consumer (the module being reset, or a module managing when a sub-
11 ordinate module is reset). This binding exists to represent the provider and
14 A reset signal is represented by the phandle of the provider, plus a reset
15 specifier - a list of DT cells that represents the reset signal within the
16 provider. The length (number of cells) and semantics of the reset specifier
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| D | ti-syscon-reset.txt | 1 TI SysCon Reset Controller
4 Almost all SoCs have hardware modules that require reset control in addition
5 to clock and power control for their functionality. The reset control is
12 A SysCon Reset Controller node defines a device that uses a syscon node
13 and provides reset management functionality for various hardware modules
16 SysCon Reset Controller Node
18 Each of the reset provider/controller nodes should be a child of a syscon
27 "ti,syscon-reset"
28 - #reset-cells : Should be 1. Please see the reset consumer node below
30 - ti,reset-bits : Contains the reset control register information
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| D | socionext,uniphier-glue-reset.yaml | 4 $id: http://devicetree.org/schemas/reset/socionext,uniphier-glue-reset.yaml#
7 title: Socionext UniPhier peripheral core reset in glue layer
10 Some peripheral core reset belongs to its own glue layer. Before using
11 this core reset, it is necessary to control the clocks and resets to
21 - socionext,uniphier-pro4-usb3-reset
22 - socionext,uniphier-pro5-usb3-reset
23 - socionext,uniphier-pxs2-usb3-reset
24 - socionext,uniphier-ld20-usb3-reset
25 - socionext,uniphier-pxs3-usb3-reset
26 - socionext,uniphier-nx1-usb3-reset
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| D | xlnx,zynqmp-reset.yaml | 4 $id: http://devicetree.org/schemas/reset/xlnx,zynqmp-reset.yaml#
7 title: Zynq UltraScale+ MPSoC and Versal reset
15 The PS reset subsystem is responsible for handling the external reset
16 input to the device and that all internal reset requirements are met
19 Please also refer to reset.txt in this directory for common reset
20 controller binding usage. Device nodes that need access to reset
21 lines should specify them as a reset phandle in their corresponding
22 node as specified in reset.txt.
24 For list of all valid reset indices for Zynq UltraScale+ MPSoC
25 <dt-bindings/reset/xlnx-zynqmp-resets.h>
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| D | amlogic,meson-reset.yaml | 5 $id: http://devicetree.org/schemas/reset/amlogic,meson-reset.yaml#
8 title: Amlogic Meson SoC Reset Controller
16 - amlogic,meson8b-reset # Reset Controller on Meson8b and compatible SoCs
17 - amlogic,meson-gxbb-reset # Reset Controller on GXBB and compatible SoCs
18 - amlogic,meson-axg-reset # Reset Controller on AXG and compatible SoCs
19 - amlogic,meson-a1-reset # Reset Controller on A1 and compatible SoCs
20 - amlogic,meson-s4-reset # Reset Controller on S4 and compatible SoCs
25 "#reset-cells":
31 - "#reset-cells"
37 reset-controller@c884404 {
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| D | snps,hsdk-reset.txt | 1 Binding for the Synopsys HSDK reset controller
3 This binding uses the common reset binding[1].
5 [1] Documentation/devicetree/bindings/reset/reset.txt
8 - compatible: should be "snps,hsdk-reset".
9 - reg: should always contain 2 pairs address - length: first for reset
10 configuration register and second for corresponding SW reset and status bits
12 - #reset-cells: from common reset binding; Should always be set to 1.
15 reset: reset@880 {
16 compatible = "snps,hsdk-reset";
17 #reset-cells = <1>;
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| D | img,pistachio-reset.txt | 1 Pistachio Reset Controller
4 This binding describes a reset controller device that is used to enable and
5 disable individual IP blocks within the Pistachio SoC using "soft reset"
8 The actual action taken when soft reset is asserted is hardware dependent.
13 Please refer to Documentation/devicetree/bindings/reset/reset.txt
14 for common reset controller binding usage.
18 - compatible: Contains "img,pistachio-reset"
20 - #reset-cells: Contains 1
31 pistachio_reset: reset-controller {
32 compatible = "img,pistachio-reset";
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| /Linux-v6.6/drivers/reset/ |
| D | Kconfig | 6 bool "Reset Controller Support"
9 Generic Reset Controller support.
11 This framework is designed to abstract reset handling of devices
12 via GPIOs or SoC-internal reset controller modules.
19 tristate "Altera Arria10 System Resource Reset"
22 This option enables support for the external reset functions for
26 bool "AR71xx Reset Driver" if COMPILE_TEST
29 This enables the ATH79 reset controller driver that supports the
30 AR71xx SoC reset controller.
33 bool "AXS10x Reset Driver" if COMPILE_TEST
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| D | Makefile | 7 obj-$(CONFIG_RESET_A10SR) += reset-a10sr.o
8 obj-$(CONFIG_RESET_ATH79) += reset-ath79.o
9 obj-$(CONFIG_RESET_AXS10X) += reset-axs10x.o
10 obj-$(CONFIG_RESET_BCM6345) += reset-bcm6345.o
11 obj-$(CONFIG_RESET_BERLIN) += reset-berlin.o
12 obj-$(CONFIG_RESET_BRCMSTB) += reset-brcmstb.o
13 obj-$(CONFIG_RESET_BRCMSTB_RESCAL) += reset-brcmstb-rescal.o
14 obj-$(CONFIG_RESET_HSDK) += reset-hsdk.o
15 obj-$(CONFIG_RESET_IMX7) += reset-imx7.o
16 obj-$(CONFIG_RESET_INTEL_GW) += reset-intel-gw.o
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| D | reset-ti-sci.c | 3 * Texas Instrument's System Control Interface (TI-SCI) reset driver
14 #include <linux/reset-controller.h>
18 * struct ti_sci_reset_control - reset control structure
20 * @reset_mask: reset mask to use for toggling reset
30 * struct ti_sci_reset_data - reset controller information structure
31 * @rcdev: reset controller entity
32 * @dev: reset controller device pointer
34 * @idr: idr structure for mapping ids to reset control structures
47 * ti_sci_reset_set() - program a device's reset
48 * @rcdev: reset controller entity
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| D | reset-ti-syscon.c | 3 * TI SYSCON regmap reset driver
15 #include <linux/reset-controller.h>
17 #include <dt-bindings/reset/ti-syscon.h>
20 * struct ti_syscon_reset_control - reset control structure
21 * @assert_offset: reset assert control register offset from syscon base
22 * @assert_bit: reset assert bit in the reset assert control register
23 * @deassert_offset: reset deassert control register offset from syscon base
24 * @deassert_bit: reset deassert bit in the reset deassert control register
25 * @status_offset: reset status register offset from syscon base
26 * @status_bit: reset status bit in the reset status register
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| D | core.c | 3 * Reset Controller framework
16 #include <linux/reset.h>
17 #include <linux/reset-controller.h>
27 * struct reset_control - a reset control
28 * @rcdev: a pointer to the reset controller device
29 * this reset control belongs to
30 * @list: list entry for the rcdev's reset controller list
31 * @id: ID of the reset controller in the reset
36 * @array: Is this an array of reset controls (1)?
37 * @deassert_count: Number of times this reset line has been deasserted
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| D | reset-scmi.c | 3 * ARM System Control and Management Interface (ARM SCMI) reset driver
11 #include <linux/reset-controller.h>
17 * struct scmi_reset_data - reset controller information structure
18 * @rcdev: reset controller entity
30 * scmi_reset_assert() - assert device reset
31 * @rcdev: reset controller entity
32 * @id: ID of the reset to be asserted
34 * This function implements the reset driver op to assert a device's reset
48 * scmi_reset_deassert() - deassert device reset
49 * @rcdev: reset controller entity
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| /Linux-v6.6/drivers/accel/habanalabs/include/gaudi2/ |
| D | gaudi2_async_ids_map_extended.h | 27 int reset; member
32 { .fc_id = 0, .cpu_id = 0, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
34 { .fc_id = 1, .cpu_id = 1, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
36 { .fc_id = 2, .cpu_id = 2, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
38 { .fc_id = 3, .cpu_id = 3, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
40 { .fc_id = 4, .cpu_id = 4, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
42 { .fc_id = 5, .cpu_id = 5, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
44 { .fc_id = 6, .cpu_id = 6, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
46 { .fc_id = 7, .cpu_id = 7, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
48 { .fc_id = 8, .cpu_id = 8, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
[all …]
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| /Linux-v6.6/drivers/power/reset/ |
| D | at91-reset.c | 2 * Atmel AT91 SAM9 & SAMA5 SoCs reset code
20 #include <linux/reset-controller.h>
26 #include <dt-bindings/reset/sama7g5-reset.h>
28 #define AT91_RSTC_CR 0x00 /* Reset Controller Control Register */
29 #define AT91_RSTC_PROCRST BIT(0) /* Processor Reset */
30 #define AT91_RSTC_PERRST BIT(2) /* Peripheral Reset */
31 #define AT91_RSTC_EXTRST BIT(3) /* External Reset */
34 #define AT91_RSTC_SR 0x04 /* Reset Controller Status Register */
35 #define AT91_RSTC_URSTS BIT(0) /* User Reset Status */
36 #define AT91_RSTC_RSTTYP GENMASK(10, 8) /* Reset Type */
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| /Linux-v6.6/drivers/net/ethernet/intel/i40e/ |
| D | i40e_register.h | 9 #define I40E_PF_ARQBAH 0x00080180 /* Reset: EMPR */
10 #define I40E_PF_ARQBAL 0x00080080 /* Reset: EMPR */
11 #define I40E_PF_ARQH 0x00080380 /* Reset: EMPR */
14 #define I40E_PF_ARQLEN 0x00080280 /* Reset: EMPR */
23 #define I40E_PF_ARQT 0x00080480 /* Reset: EMPR */
24 #define I40E_PF_ATQBAH 0x00080100 /* Reset: EMPR */
25 #define I40E_PF_ATQBAL 0x00080000 /* Reset: EMPR */
26 #define I40E_PF_ATQH 0x00080300 /* Reset: EMPR */
27 #define I40E_PF_ATQLEN 0x00080200 /* Reset: EMPR */
36 #define I40E_PF_ATQT 0x00080400 /* Reset: EMPR */
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| /Linux-v6.6/drivers/infiniband/hw/irdma/ |
| D | i40iw_hw.h | 5 #define I40E_VFPE_CQPTAIL1 0x0000A000 /* Reset: VFR */
6 #define I40E_VFPE_CQPDB1 0x0000BC00 /* Reset: VFR */
7 #define I40E_VFPE_CCQPSTATUS1 0x0000B800 /* Reset: VFR */
8 #define I40E_VFPE_CCQPHIGH1 0x00009800 /* Reset: VFR */
9 #define I40E_VFPE_CCQPLOW1 0x0000AC00 /* Reset: VFR */
10 #define I40E_VFPE_CQARM1 0x0000B400 /* Reset: VFR */
11 #define I40E_VFPE_CQACK1 0x0000B000 /* Reset: VFR */
12 #define I40E_VFPE_AEQALLOC1 0x0000A400 /* Reset: VFR */
13 #define I40E_VFPE_CQPERRCODES1 0x00009C00 /* Reset: VFR */
14 #define I40E_VFPE_WQEALLOC1 0x0000C000 /* Reset: VFR */
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| /Linux-v6.6/include/linux/ |
| D | reset.h | 14 * struct reset_control_bulk_data - Data used for bulk reset control operations.
16 * @id: reset control consumer ID
17 * @rstc: struct reset_control * to store the associated reset control
19 * The reset APIs provide a series of reset_control_bulk_*() API calls as
20 * a convenience to consumers which require multiple reset controls.
223 * to a reset controller.
224 * @dev: device to be reset by the controller
225 * @id: reset line name
232 * reset-controls.
244 * multiple reset controllers.
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| D | reset-controller.h | 10 * struct reset_control_ops - reset controller driver callbacks
12 * @reset: for self-deasserting resets, does all necessary
13 * things to reset the device
14 * @assert: manually assert the reset line, if supported
15 * @deassert: manually deassert the reset line, if supported
16 * @status: return the status of the reset line, if supported
19 int (*reset)(struct reset_controller_dev *rcdev, unsigned long id); member
32 * @list: internal list of all reset lookup entries
33 * @provider: name of the reset controller device controlling this reset line
34 * @index: ID of the reset controller in the reset controller device
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| /Linux-v6.6/Documentation/devicetree/bindings/power/reset/ |
| D | keystone-reset.txt | 1 * Device tree bindings for Texas Instruments keystone reset
3 This node is intended to allow SoC reset in case of software reset
6 The Keystone SoCs can contain up to 4 watchdog timers to reset
7 SoC. Each watchdog timer event input is connected to the Reset Mux
8 block. The Reset Mux block can be configured to cause reset or not.
10 Additionally soft or hard reset can be configured.
14 - compatible: ti,keystone-reset
18 reset control registers.
26 - ti,soft-reset: Boolean option indicating soft reset.
27 By default hard reset is used.
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| /Linux-v6.6/drivers/clk/visconti/ |
| D | reset.c | 3 * Toshiba Visconti ARM SoC reset controller
16 #include "reset.h"
25 struct visconti_reset *reset = to_visconti_reset(rcdev); in visconti_reset_assert() local
26 const struct visconti_reset_data *data = &reset->resets[id]; in visconti_reset_assert()
31 spin_lock_irqsave(reset->lock, flags); in visconti_reset_assert()
32 ret = regmap_update_bits(reset->regmap, data->rson_offset, rst, rst); in visconti_reset_assert()
33 spin_unlock_irqrestore(reset->lock, flags); in visconti_reset_assert()
40 struct visconti_reset *reset = to_visconti_reset(rcdev); in visconti_reset_deassert() local
41 const struct visconti_reset_data *data = &reset->resets[id]; in visconti_reset_deassert()
46 spin_lock_irqsave(reset->lock, flags); in visconti_reset_deassert()
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| /Linux-v6.6/drivers/net/ethernet/ibm/emac/ |
| D | emac.h | 30 u32 mr1; /* Reset */
33 u32 rmr; /* Reset */
35 u32 iser; /* Reset */
36 u32 iahr; /* Reset, R, T */
37 u32 ialr; /* Reset, R, T */
38 u32 vtpid; /* Reset, R, T */
39 u32 vtci; /* Reset, R, T */
40 u32 ptr; /* Reset, T */
44 u32 iaht1; /* Reset, R */
45 u32 iaht2; /* Reset, R */
[all …]
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