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/Linux-v5.10/drivers/clk/qcom/
Dclk-regmap.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
11 #include "clk-regmap.h"
14 * clk_is_enabled_regmap - standard is_enabled() for regmap users
24 struct clk_regmap *rclk = to_clk_regmap(hw); in clk_is_enabled_regmap() local
28 ret = regmap_read(rclk->regmap, rclk->enable_reg, &val); in clk_is_enabled_regmap()
32 if (rclk->enable_is_inverted) in clk_is_enabled_regmap()
33 return (val & rclk->enable_mask) == 0; in clk_is_enabled_regmap()
35 return (val & rclk->enable_mask) != 0; in clk_is_enabled_regmap()
40 * clk_enable_regmap - standard enable() for regmap users
[all …]
Dclk-regmap.h1 /* SPDX-License-Identifier: GPL-2.0 */
7 #include <linux/clk-provider.h>
12 * struct clk_regmap - regmap supporting clock
13 * @hw: handle between common and hardware-specific interfaces
36 int devm_clk_register_regmap(struct device *dev, struct clk_regmap *rclk);
/Linux-v5.10/sound/soc/samsung/
Darndale.c1 // SPDX-License-Identifier: GPL-2.0+
13 #include <sound/soc-dapm.h>
27 unsigned long rclk; in arndale_rt5631_hw_params() local
31 rclk = params_rate(params) * rfs; in arndale_rt5631_hw_params()
44 ret = snd_soc_dai_set_sysclk(codec_dai, 0, rclk, SND_SOC_CLOCK_OUT); in arndale_rt5631_hw_params()
60 unsigned int rfs, rclk; in arndale_wm1811_hw_params() local
70 rclk = params_rate(params) * rfs; in arndale_wm1811_hw_params()
75 * samsung/clk-exynos5250.c for list of available EPLL rates). in arndale_wm1811_hw_params()
80 rclk + 1, SND_SOC_CLOCK_IN); in arndale_wm1811_hw_params()
89 DAILINK_COMP_ARRAY(COMP_CODEC(NULL, "rt5631-aif1")),
[all …]
Dsnow.c1 // SPDX-License-Identifier: GPL-2.0
34 struct snow_priv *priv = snd_soc_card_get_drvdata(rtd->card); in snow_card_hw_params()
36 unsigned long int rclk; in snow_card_hw_params() local
37 long int freq = -EINVAL; in snow_card_hw_params()
42 dev_err(rtd->card->dev, "Invalid bit-width: %d\n", bitwidth); in snow_card_hw_params()
47 dev_err(rtd->card->dev, "Unsupported bit-width: %d\n", bitwidth); in snow_card_hw_params()
48 return -EINVAL; in snow_card_hw_params()
73 return -EINVAL; in snow_card_hw_params()
76 rclk = params_rate(params) * rfs; in snow_card_hw_params()
80 if ((pll_rate[i] - rclk * psr) <= 2) { in snow_card_hw_params()
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Ds3c-i2s-v2.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * ALSA Soc Audio Layer - S3C_I2SV2 I2S driver
11 * Samsung SoC devices which is unofficially named I2S-V2. Currently the
28 * bridge/break RCLK signal and external Xi2sCDCLK pin.
33 * struct s3c_i2sv2_info - S3C I2S-V2 information
36 * @feature: Set of bit-flags indicating features of the controller.
80 * s3c_i2sv2_probe - probe for i2s device helper
89 * s3c_i2sv2_cleanup - cleanup resources allocated in s3c_i2sv2_probe
96 * s3c_i2sv2_register_component - register component and dai with soc core
/Linux-v5.10/Documentation/devicetree/bindings/net/
Dftgmac100.txt4 - compatible: "faraday,ftgmac100"
10 - "aspeed,ast2400-mac"
11 - "aspeed,ast2500-mac"
12 - "aspeed,ast2600-mac"
14 - reg: Address and length of the register set for the device
15 - interrupts: Should contain ethernet controller interrupt
18 - phy-mode: See ethernet.txt file in the same directory. If the property is
21 - use-ncsi: Use the NC-SI stack instead of an MDIO PHY. Currently assumes
22 rmii (100bT) but kept as a separate property in case NC-SI grows support
24 - no-hw-checksum: Used to disable HW checksum support. Here for backward
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/Linux-v5.10/drivers/slimbus/
Dqcom-ctrl.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2011-2017, The Linux Foundation
88 /* Resource group info for manager, and non-ported generic device-components */
116 struct clk *rclk; member
125 __iowrite32_copy(ctrl->base + tx_reg, buf, count); in qcom_slim_queue_tx()
136 spin_lock_irqsave(&ctrl->rx.lock, flags); in slim_alloc_rxbuf()
137 if ((ctrl->rx.tail + 1) % ctrl->rx.n == ctrl->rx.head) { in slim_alloc_rxbuf()
138 spin_unlock_irqrestore(&ctrl->rx.lock, flags); in slim_alloc_rxbuf()
139 dev_err(ctrl->dev, "RX QUEUE full!"); in slim_alloc_rxbuf()
142 idx = ctrl->rx.tail; in slim_alloc_rxbuf()
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/Linux-v5.10/arch/arm/boot/dts/
Daspeed-bmc-portwell-neptune.dts1 // SPDX-License-Identifier: GPL-2.0
3 /dts-v1/;
5 #include "aspeed-g5.dtsi"
6 #include <dt-bindings/gpio/aspeed-gpio.h>
10 compatible = "portwell,neptune-bmc", "aspeed,ast2500";
16 stdout-path = &uart5;
25 compatible = "gpio-leds";
29 default-state = "on";
34 linux,default-trigger = "heartbeat";
40 // postcode3-7 are GPIOH3-H7
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Daspeed-bmc-facebook-yamp.dts1 // SPDX-License-Identifier: GPL-2.0+
3 /dts-v1/;
5 #include "ast2500-facebook-netbmc-common.dtsi"
9 compatible = "facebook,yamp-bmc", "aspeed,ast2500";
23 stdout-path = &uart5;
30 pinctrl-names = "default";
31 pinctrl-0 = <&pinctrl_txd2_default
37 use-ncsi;
38 pinctrl-names = "default";
39 pinctrl-0 = <&pinctrl_rmii1_default>;
[all …]
Daspeed-bmc-intel-s2600wf.dts1 // SPDX-License-Identifier: GPL-2.0
3 /dts-v1/;
5 #include "aspeed-g5.dtsi"
9 compatible = "intel,s2600wf-bmc", "aspeed,ast2500";
12 stdout-path = &uart5;
20 reserved-memory {
21 #address-cells = <1>;
22 #size-cells = <1>;
26 no-map;
31 iio-hwmon {
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Daspeed-bmc-inspur-on5263m5.dts1 // SPDX-License-Identifier: GPL-2.0
3 /dts-v1/;
5 #include "aspeed-g5.dtsi"
6 #include <dt-bindings/gpio/aspeed-gpio.h>
10 compatible = "inspur,on5263m5-bmc", "aspeed,ast2500";
13 stdout-path = &uart5;
21 reserved-memory {
22 #address-cells = <1>;
23 #size-cells = <1>;
27 no-map;
[all …]
Daspeed-bmc-arm-stardragon4800-rep2.dts1 // SPDX-License-Identifier: GPL-2.0+
2 /dts-v1/;
4 #include "aspeed-g5.dtsi"
5 #include <dt-bindings/gpio/aspeed-gpio.h>
9 compatible = "hxt,stardragon4800-rep2-bmc", "aspeed,ast2500";
12 stdout-path = &uart5;
20 iio-hwmon {
21 compatible = "iio-hwmon";
22 io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>,
26 iio-hwmon-battery {
[all …]
Daspeed-bmc-amd-ethanolx.dts1 // SPDX-License-Identifier: GPL-2.0
4 /dts-v1/;
6 #include "aspeed-g5.dtsi"
7 #include <dt-bindings/gpio/aspeed-gpio.h>
11 compatible = "amd,ethanolx-bmc", "aspeed,ast2500";
21 stdout-path = &uart5;
25 compatible = "gpio-leds";
35 iio-hwmon {
36 compatible = "iio-hwmon";
37 io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, <&adc 4>;
[all …]
/Linux-v5.10/Documentation/devicetree/bindings/mmc/
Dsdhci-msm.txt1 * Qualcomm SDHCI controller (sdhci-msm)
4 and the properties used by the sdhci-msm driver.
7 - compatible: Should contain a SoC-specific string and a IP version string:
9 "qcom,sdhci-msm-v4" for sdcc versions less than 5.0
10 "qcom,sdhci-msm-v5" for sdcc version 5.0
13 string is added to support this change - "qcom,sdhci-msm-v5".
15 "qcom,apq8084-sdhci", "qcom,sdhci-msm-v4"
16 "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"
17 "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4"
18 "qcom,msm8992-sdhci", "qcom,sdhci-msm-v4"
[all …]
Dexynos-dw-mshc.txt7 by synopsys-dw-mshc.txt and the properties used by the Samsung Exynos specific
13 - "samsung,exynos4210-dw-mshc": for controllers with Samsung Exynos4210
15 - "samsung,exynos4412-dw-mshc": for controllers with Samsung Exynos4412
17 - "samsung,exynos5250-dw-mshc": for controllers with Samsung Exynos5250
19 - "samsung,exynos5420-dw-mshc": for controllers with Samsung Exynos5420
21 - "samsung,exynos7-dw-mshc": for controllers with Samsung Exynos7
23 - "samsung,exynos7-dw-mshc-smu": for controllers with Samsung Exynos7
26 * samsung,dw-mshc-ciu-div: Specifies the divider value for the card interface
30 * samsung,dw-mshc-sdr-timing: Specifies the value of CIU clock phase shift value
35 * samsung,dw-mshc-ddr-timing: Specifies the value of CUI clock phase shift value
[all …]
/Linux-v5.10/include/dt-bindings/sound/
Dsamsung-i2s.h1 /* SPDX-License-Identifier: GPL-2.0 */
11 #define CLK_I2S_RCLK_PSR 2 /* the RCLK prescaler divider clock
/Linux-v5.10/Documentation/devicetree/bindings/clock/
Dbaikal,bt1-ccu-pll.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/clock/baikal,bt1-ccu-pll.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Baikal-T1 Clock Control Unit PLL
11 - Serge Semin <fancer.lancer@gmail.com>
14 Clocks Control Unit is the core of Baikal-T1 SoC System Controller
18 IP-blocks or to groups of blocks (clock domains). The transformation is done
19 by means of PLLs and gateable/non-gateable dividers embedded into the CCU.
23 2) PLLs clocks generators (PLLs) - described in this binding file.
[all …]
/Linux-v5.10/drivers/clk/
Dclk-ast2600.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 #define pr_fmt(fmt) "clk-ast2600: " fmt
14 #include <dt-bindings/clock/ast2600-clock.h>
16 #include "clk-aspeed.h"
62 [ASPEED_CLK_GATE_MCLK] = { 0, -1, "mclk-gate", "mpll", CLK_IS_CRITICAL }, /* SDRAM */
63 [ASPEED_CLK_GATE_ECLK] = { 1, -1, "eclk-gate", "eclk", 0 }, /* Video Engine */
64 [ASPEED_CLK_GATE_GCLK] = { 2, 7, "gclk-gate", NULL, 0 }, /* 2D engine */
65 /* vclk parent - dclk/d1clk/hclk/mclk */
66 [ASPEED_CLK_GATE_VCLK] = { 3, 6, "vclk-gate", NULL, 0 }, /* Video Capture */
67 [ASPEED_CLK_GATE_BCLK] = { 4, 8, "bclk-gate", "bclk", 0 }, /* PCIe/PCI */
[all …]
Dclk-aspeed.c1 // SPDX-License-Identifier: GPL-2.0+
4 #define pr_fmt(fmt) "clk-aspeed: " fmt
13 #include <dt-bindings/clock/aspeed-clock.h>
15 #include "clk-aspeed.h"
49 [ASPEED_CLK_GATE_ECLK] = { 0, 6, "eclk-gate", "eclk", 0 }, /* Video Engine */
50 [ASPEED_CLK_GATE_GCLK] = { 1, 7, "gclk-gate", NULL, 0 }, /* 2D engine */
51 [ASPEED_CLK_GATE_MCLK] = { 2, -1, "mclk-gate", "mpll", CLK_IS_CRITICAL }, /* SDRAM */
52 [ASPEED_CLK_GATE_VCLK] = { 3, -1, "vclk-gate", NULL, 0 }, /* Video Capture */
53 [ASPEED_CLK_GATE_BCLK] = { 4, 8, "bclk-gate", "bclk", CLK_IS_CRITICAL }, /* PCIe/PCI */
54 [ASPEED_CLK_GATE_DCLK] = { 5, -1, "dclk-gate", NULL, CLK_IS_CRITICAL }, /* DAC */
[all …]
/Linux-v5.10/arch/arm64/boot/dts/qcom/
Dqcs404-evb.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
17 stdout-path = "serial0";
20 vph_pwr: vph-pwr-regulator {
21 compatible = "regulator-fixed";
22 regulator-name = "vph_pwr";
23 regulator-always-on;
24 regulator-boot-on;
[all …]
/Linux-v5.10/Documentation/devicetree/bindings/mtd/
Dcadence-quadspi.txt4 - compatible : should be one of the following:
5 Generic default - "cdns,qspi-nor".
6 For TI 66AK2G SoC - "ti,k2g-qspi", "cdns,qspi-nor".
7 For TI AM654 SoC - "ti,am654-ospi", "cdns,qspi-nor".
8 - reg : Contains two entries, each of which is a tuple consisting of a
12 - interrupts : Unit interrupt specifier for the controller interrupt.
13 - clocks : phandle to the Quad SPI clock.
14 - cdns,fifo-depth : Size of the data FIFO in words.
15 - cdns,fifo-width : Bus width of the data FIFO in bytes.
16 - cdns,trigger-address : 32-bit indirect AHB trigger address.
[all …]
/Linux-v5.10/drivers/clk/renesas/
Drcar-gen3-cpg.c1 // SPDX-License-Identifier: GPL-2.0
3 * R-Car Gen3 Clock Pulse Generator
5 * Copyright (C) 2015-2018 Glider bvba
8 * Based on clk-rcar-gen3.c
16 #include <linux/clk-provider.h>
25 #include "renesas-cpg-mssr.h"
26 #include "rcar-gen3-cpg.h"
32 #define CPG_RCKCR_CKSEL BIT(15) /* RCLK Clock Source Select */
63 csn->saved = readl(csn->reg); in cpg_simple_notifier_call()
67 writel(csn->saved, csn->reg); in cpg_simple_notifier_call()
[all …]
/Linux-v5.10/drivers/net/ethernet/faraday/
Dftgmac100.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * (C) Copyright 2009-2011 Faraday Technology
6 * Po-Yu Chuang <ratbert@faraday-tech.com>
12 #include <linux/dma-mapping.h>
93 struct clk *rclk; member
116 struct net_device *netdev = priv->netdev; in ftgmac100_reset_mac()
120 iowrite32(maccr, priv->base + FTGMAC100_OFFSET_MACCR); in ftgmac100_reset_mac()
122 priv->base + FTGMAC100_OFFSET_MACCR); in ftgmac100_reset_mac()
126 maccr = ioread32(priv->base + FTGMAC100_OFFSET_MACCR); in ftgmac100_reset_mac()
134 return -EIO; in ftgmac100_reset_mac()
[all …]
/Linux-v5.10/arch/mips/alchemy/common/
Dclock.c1 // SPDX-License-Identifier: GPL-2.0
8 * - Root source, usually 12MHz supplied by an external crystal
9 * - 3 PLLs which generate multiples of root rate [AUX, CPU, AUX2]
12 * - 6 clock dividers with:
18 * - up to 6 "internal" (fixed) consumers which:
24 * - sysbus clock: CPU core clock (CPUPLL) divided by 2, 3 or 4.
25 * depends on board design and should be set by bootloader, read-only.
26 * - peripheral clock: half the rate of sysbus clock, source for a lot
27 * of peripheral blocks, read-only.
28 * - memory clock: clk rate to main memory chips, depends on board
[all …]
/Linux-v5.10/Documentation/devicetree/bindings/hwmon/
Dbaikal,bt1-pvt.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/hwmon/baikal,bt1-pvt.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Baikal-T1 PVT Sensor
11 - Serge Semin <fancer.lancer@gmail.com>
14 Baikal-T1 SoC provides an embedded process, voltage and temperature
17 which may cause the system instability and even damages. The IP-block
19 control wrapper, which provides a MMIO registers-based access to the
20 sensor core functionality (APB3-bus based) and exposes an additional
[all …]

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