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/Linux-v6.1/arch/riscv/boot/dts/starfive/
Djh7100.dtsi144 rstgen: reset-controller@11840000 { label
156 resets = <&rstgen JH7100_RSTN_I2C0_APB>;
169 resets = <&rstgen JH7100_RSTN_I2C1_APB>;
182 resets = <&rstgen JH7100_RSTN_GPIO_APB>;
196 resets = <&rstgen JH7100_RSTN_UART2_APB>;
209 resets = <&rstgen JH7100_RSTN_UART3_APB>;
222 resets = <&rstgen JH7100_RSTN_I2C2_APB>;
235 resets = <&rstgen JH7100_RSTN_I2C3_APB>;
/Linux-v6.1/Documentation/devicetree/bindings/clock/
Dnvidia,tegra20-car.yaml15 Tegra's clocks, and setting their rates. It comprises CLKGEN and RSTGEN units.
25 RSTGEN provides the registers needed to control resetting of each block in
Dnvidia,tegra124-car.yaml15 Tegra's clocks, and setting their rates. It comprises CLKGEN and RSTGEN units.
25 RSTGEN provides the registers needed to control resetting of each block in