Searched full:rams (Results 1 – 25 of 31) sorted by relevance
12
24 …t counts any correctable or uncorrectable memory error (ECC or parity) in the protected core RAMs",
8 …t counts any correctable or uncorrectable memory error (ECC or parity) in the protected core RAMs",
19 instruction RAMs, some internal peripheral modules to facilitate industrial35 acts on a primary Data RAM (there are usually 2 Data RAMs) at its address92 The various Data RAMs within a single PRU-ICSS unit are represented as a
165 #define XCHAL_NUM_INSTRAM 0 /* number of core instr. RAMs */167 #define XCHAL_NUM_DATARAM 0 /* number of core data RAMs */168 #define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/
263 Single Cycle RAMS to store Fast Path Code273 Single Cycle RAMS to store Fast Path Data
172 #define XCHAL_NUM_INSTRAM 0 /* number of core instr. RAMs */174 #define XCHAL_NUM_DATARAM 0 /* number of core data RAMs */175 #define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/
185 #define XCHAL_NUM_INSTRAM 0 /* number of core instr. RAMs */187 #define XCHAL_NUM_DATARAM 0 /* number of core data RAMs */188 #define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/
5 tristate "I2C EEPROMs / RAMs / ROMs from most vendors"
154 This microcode relocates SMC1 and SMC2 parameter RAMs at
218 #define XCHAL_NUM_INSTRAM 0 /* number of core instr. RAMs */220 #define XCHAL_NUM_DATARAM 0 /* number of core data RAMs */221 #define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/
242 * Custom function to translate a DSP device address (internal RAMs only) to a243 * kernel virtual address. The DSPs can access their RAMs at either an internal
224 * internal RAMs. The .prepare() ops is invoked by remoteproc core before any350 * Custom function to translate a DSP device address (internal RAMs only) to a351 * kernel virtual address. The DSPs can access their RAMs at either an internal
724 * translation (device address to kernel virtual address) for internal RAMs
284 #define XCHAL_NUM_INSTRAM 0 /* number of core instr. RAMs */286 #define XCHAL_NUM_DATARAM 0 /* number of core data RAMs */287 #define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/
285 #define XCHAL_NUM_INSTRAM 0 /* number of core instr. RAMs */287 #define XCHAL_NUM_DATARAM 0 /* number of core data RAMs */288 #define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/
242 #define XCHAL_NUM_INSTRAM 0 /* number of core instr. RAMs */244 #define XCHAL_NUM_DATARAM 0 /* number of core data RAMs */245 #define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/
284 #define XCHAL_NUM_INSTRAM 1 /* number of core instr. RAMs */286 #define XCHAL_NUM_DATARAM 1 /* number of core data RAMs */287 #define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/
93 description: Cycles of latency for Dirty RAMs. This is a single cell.
107 any RAMs)
264 /* Disable plane and power down most RAMs and FIFOs */ in armada_drm_primary_plane_atomic_disable()
459 /* Insert into Action and policer RAMs now */ in bcm_sf2_cfp_ipv4_rule_set()761 /* Insert into Action and policer RAMs now */ in bcm_sf2_cfp_ipv6_rule_set()817 /* Insert into Action and policer RAMs now, set chain ID to in bcm_sf2_cfp_ipv6_rule_set()
24 /* 1 = BIST and set all USB RAMs to 0x0, 0 = BIST */
578 * Some systems share FTLB RAMs between threads within a core (siblings in
240 * the clock and write enable to the S/PDIF SRC RAMs is not properly
395 dev_info(fei->dev, "RAMs supported by C8SECTPFE: %d\n", hw->num_ram); in c8sectpfe_getconfig()
