| /Linux-v6.1/Documentation/livepatch/ |
| D | callbacks.rst | 42 * Post-patch
48 active), used to clean up post-patch callback
51 * Post-unpatch
61 symmetry: pre-patch callbacks have a post-unpatch counterpart and
62 post-patch callbacks have a pre-unpatch counterpart. An unpatch
90 No post-patch, pre-unpatch, or post-unpatch callbacks will be executed
96 will only occur if their corresponding post-patch callback executed).
100 only the post-unpatch callback will be called.
118 patch the data *after* patching is complete with a post-patch callback,
126 may be possible to implement similar updates via pre/post-patch
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| /Linux-v6.1/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/ |
| D | gm200.c | 82 pmu_load(struct nv50_devinit *init, u8 type, bool post, in pmu_load() argument
92 if (!post) in pmu_load()
109 gm200_devinit_preos(struct nv50_devinit *init, bool post) in gm200_devinit_preos() argument
114 pmu_load(init, 0x01, post, NULL, NULL); in gm200_devinit_preos()
118 gm200_devinit_post(struct nvkm_devinit *base, bool post) in gm200_devinit_post() argument
135 ret = pmu_load(init, 0x04, post, &exec, &args); in gm200_devinit_post()
142 if (post) { in gm200_devinit_post()
150 if (post) { in gm200_devinit_post()
158 if (post) { in gm200_devinit_post()
168 gm200_devinit_preos(init, post); in gm200_devinit_post()
[all …]
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| D | base.c | 62 if (init && init->func->post) in nvkm_devinit_post()
63 ret = init->func->post(init, init->post); in nvkm_devinit_post()
74 init->post = true; in nvkm_devinit_fini()
86 /* Override the post flag during the first call if NvForcePost is set */ in nvkm_devinit_preinit()
88 init->post = init->force_post; in nvkm_devinit_preinit()
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| D | nv50.c | 101 * missing, assume it's a secondary gpu which requires post in nv50_devinit_preinit()
103 if (!base->post) { in nv50_devinit_preinit()
106 base->post = true; in nv50_devinit_preinit()
112 if (!base->post) { in nv50_devinit_preinit()
116 base->post = true; in nv50_devinit_preinit()
137 while (init->base.post && dcb_outp_parse(bios, i, &ver, &hdr, &outp)) { in nv50_devinit_init()
168 .post = nv04_devinit_post,
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| D | tu102.c | 69 tu102_devinit_post(struct nvkm_devinit *base, bool post) in tu102_devinit_post() argument
72 gm200_devinit_preos(init, post); in tu102_devinit_post()
79 .post = tu102_devinit_post,
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| /Linux-v6.1/tools/testing/selftests/livepatch/ |
| D | test-callbacks.sh | 22 # according to the klp_patch, their post-patch callbacks run and the
26 # unpatching transition starts. klp_objects are reverted, post-patch
67 # - On livepatch enable, only pre/post-patch callbacks are executed for
71 # pre/post-patch callbacks are executed.
74 # $MOD_TARGET) pre/post-unpatch callbacks are executed.
119 # post-unpatch callbacks are executed when this occurs.
121 # - When the livepatch is disabled, pre and post-unpatch callbacks are
166 # pre/post-patch callbacks are executed.
170 # post-unpatch callbacks are executed when this occurs.
213 # - As expected, only pre/post-(un)patch handlers are executed for
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| /Linux-v6.1/drivers/media/i2c/cx25840/ |
| D | cx25840-audio.c | 39 * VID_PLL Integer = 0x0f, VID_PLL Post Divider = 0x04 in cx25840_set_audclk_freq()
40 * AUX_PLL Integer = 0x06, AUX PLL Post Divider = 0x10 in cx25840_set_audclk_freq()
61 * SA_MCLK_DIV = 0x10 = 384/384 * AUX_PLL post dvivider in cx25840_set_audclk_freq()
77 * VID_PLL Integer = 0x0f, VID_PLL Post Divider = 0x04 in cx25840_set_audclk_freq()
78 * AUX_PLL Integer = 0x09, AUX PLL Post Divider = 0x10 in cx25840_set_audclk_freq()
98 * SA_MCLK_DIV = 0x10 = 384/384 * AUX_PLL post dvivider in cx25840_set_audclk_freq()
114 * VID_PLL Integer = 0x0f, VID_PLL Post Divider = 0x04 in cx25840_set_audclk_freq()
115 * AUX_PLL Integer = 0x0a, AUX PLL Post Divider = 0x10 in cx25840_set_audclk_freq()
135 * SA_MCLK_DIV = 0x10 = 384/384 * AUX_PLL post dvivider in cx25840_set_audclk_freq()
153 * VID_PLL Integer = 0x0f, VID_PLL Post Divider = 0x04 in cx25840_set_audclk_freq()
[all …]
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| /Linux-v6.1/Documentation/devicetree/bindings/clock/ |
| D | keystone-pll.txt | 4 a divider and a post divider. The additional PLL IPs like ARMPLL, DDRPLL
18 - reg-names : control, multiplier and post-divider. The multiplier and
19 post-divider registers are applicable only for main pll clock
20 - fixed-postdiv : fixed post divider value. If absent, use clkod register bits
29 reg-names = "control", "multiplier", "post-divider";
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| /Linux-v6.1/drivers/clk/qcom/ |
| D | clk-alpha-pll.h | 85 * struct clk_alpha_pll_postdiv - phase locked loop (PLL) post-divider
88 * @width: width of post-divider
89 * @post_div_shift: shift to differentiate between odd & even post-divider
90 * @post_div_table: table with PLL odd and even post-divider settings
91 * @num_post_div: Number of PLL post-divider settings
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| /Linux-v6.1/drivers/media/pci/cx18/ |
| D | cx18-av-audio.c | 60 * VID_PLL Integer = 0x0f, VID_PLL Post Divider = 0x04 in set_audclk_freq()
61 * AUX_PLL Integer = 0x0d, AUX PLL Post Divider = 0x20 in set_audclk_freq()
95 * VID_PLL Integer = 0x0f, VID_PLL Post Divider = 0x04 in set_audclk_freq()
96 * AUX_PLL Integer = 0x0e, AUX PLL Post Divider = 0x18 in set_audclk_freq()
130 * VID_PLL Integer = 0x0f, VID_PLL Post Divider = 0x04 in set_audclk_freq()
131 * AUX_PLL Integer = 0x0e, AUX PLL Post Divider = 0x16 in set_audclk_freq()
167 * VID_PLL Integer = 0x0f, VID_PLL Post Divider = 0x04 in set_audclk_freq()
168 * AUX_PLL Integer = 0x0d, AUX PLL Post Divider = 0x30 in set_audclk_freq()
206 * VID_PLL Integer = 0x0f, VID_PLL Post Divider = 0x04 in set_audclk_freq()
207 * AUX_PLL Integer = 0x0e, AUX PLL Post Divider = 0x24 in set_audclk_freq()
[all …]
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| /Linux-v6.1/drivers/video/fbdev/matrox/ |
| D | matroxfb_misc.h | 9 unsigned int* in, unsigned int* feed, unsigned int* post);
13 unsigned int *post) in PLL_calcclock() argument
15 return matroxfb_PLL_calcclock(&minfo->features.pll, freq, fmax, in, feed, post); in PLL_calcclock()
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| /Linux-v6.1/tools/testing/selftests/drivers/net/netdevsim/ |
| D | devlink.sh | 106 check_value max_macs post-set 16 32
107 check_value test1 post-set false Y
111 check_value max_macs post-reload 16 16
112 check_value test1 post-reload false N
151 check_region_snapshot_count dummy post-first-snapshot 1
155 check_region_snapshot_count dummy post-second-snapshot 2
159 check_region_snapshot_count dummy post-third-snapshot 3
164 check_region_snapshot_count dummy post-first-delete 2
169 check_region_snapshot_count dummy post-first-request 3
189 check_region_snapshot_count dummy post-second-delete 2
[all …]
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| /Linux-v6.1/tools/testing/selftests/tc-testing/creating-plugins/ |
| D | AddingPlugins.txt | 23 post (the post-suite stage)
52 post-suite method using this info passed in to the pre_suite method.
82 'post'
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| /Linux-v6.1/drivers/net/ethernet/mellanox/mlx5/core/en/tc/ |
| D | post_act.c | 53 mlx5_core_warn(priv->mdev, "failed to create post action table, err: %d\n", err); in mlx5e_tc_post_act_init()
90 /* Post action rule matches on fte_id and executes original rule's tc rule action */ in mlx5e_tc_post_act_offload()
96 netdev_warn(post_act->priv->netdev, "Failed to add post action rule"); in mlx5e_tc_post_act_offload()
134 /* Splits were handled before post action */ in mlx5e_tc_post_act_add()
177 /* Allocate a header modify action to write the post action handle fte id to a register. */
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| /Linux-v6.1/drivers/gpu/drm/i915/gt/ |
| D | gen6_engine_cs.c | 18 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
24 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
28 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
33 * BEFORE the pipe-control with a post-sync op and no write-cache
45 * - Post-Sync Operation ([13] of DW1)
50 * Post-sync nonzero is what triggered this second workaround, so we
125 * TLB invalidate requires a post-sync write. in gen6_emit_flush_rcs()
200 * Post-Sync Operation field is a value of 1h or 3h." in mi_flush_dw()
307 * CS_STALL suggests at least a post-sync write. in gen7_emit_flush_rcs()
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| /Linux-v6.1/sound/core/ |
| D | pcm_timer.c | 21 unsigned long rate, mult, fsize, l, post; in snd_pcm_timer_resolution_change() local
37 post = 1; in snd_pcm_timer_resolution_change()
40 post *= 2; in snd_pcm_timer_resolution_change()
49 runtime->timer_resolution = (mult * fsize / rate) * post; in snd_pcm_timer_resolution_change()
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| /Linux-v6.1/drivers/infiniband/hw/qedr/ |
| D | qedr_roce_cm.c | 431 DP_ERR(dev, "gsi post send: failed to init header\n"); in qedr_gsi_build_header()
554 "gsi post recv: failed to post rx buffer. state is %d and not QED_ROCE_QP_STATE_RTS\n", in qedr_gsi_post_send()
560 DP_ERR(dev, "gsi post send: num_sge is too large (%d>%d)\n", in qedr_gsi_post_send()
568 "gsi post send: failed due to unsupported opcode %d\n", in qedr_gsi_post_send()
588 "gsi post send: opcode=%d, wr_id=%llx\n", wr->opcode, in qedr_gsi_post_send()
591 DP_ERR(dev, "gsi post send: failed to transmit (rc=%d)\n", rc); in qedr_gsi_post_send()
600 "gsi post send: failed second WR. Only one WR may be passed at a time\n"); in qedr_gsi_post_send()
624 "gsi post recv: failed to post rx buffer. state is %d and not QED_ROCE_QP_STATE_RTR/S\n", in qedr_gsi_post_recv()
634 "gsi post recv: failed to post rx buffer. too many sges %d>%d\n", in qedr_gsi_post_recv()
647 "gsi post recv: failed to post rx buffer (rc=%d)\n", in qedr_gsi_post_recv()
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| /Linux-v6.1/drivers/mmc/core/ |
| D | core.h | 156 * mmc_post_req - Post process a completed request
157 * @host: MMC host to post process command
158 * @mrq: MMC request to post process for
161 * Let the host post process a completed request. Post processing of
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| /Linux-v6.1/Documentation/ABI/testing/ |
| D | configfs-most | 60 configuration, the creation is post-poned until
115 configuration, the creation is post-poned until
170 configuration, the creation is post-poned until
236 configuration, the creation is post-poned until
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| /Linux-v6.1/drivers/clk/analogbits/ |
| D | wrpll-cln28hpc.c | 40 /* MIN_POST_DIVIDE_REF_FREQ: minimum post-divider reference frequency, in Hz */
43 /* MAX_POST_DIVIDE_REF_FREQ: maximum post-divider reference frequency, in Hz */
76 * on the input clock frequency after the post-R-divider @post_divr_freq.
87 WARN(1, "%s: post-divider reference freq out of range: %lu", in __wrpll_calc_filter_range()
137 * Determine a reasonable value for the PLL Q post-divider, based on the
207 * @target_rate: target PLL output clock rate (post-Q-divider)
324 * post-divider).
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| /Linux-v6.1/Documentation/devicetree/bindings/display/ |
| D | amlogic,meson-vpu.yaml | 20 D | vd2 | VIU | | Video Post | | Video Encoders |<---|-----VCLK |
37 VPP: Video Post Processing
40 The Video Post Processing is in charge of the scaling and blending of the
43 scaler and a "post-blending" to merge with the OSD Planes.
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| /Linux-v6.1/drivers/clk/ingenic/ |
| D | cgu.h | 33 * @od_shift: the number of bits to shift the post-VCO divider value by (ie.
34 * the index of the lowest bit of the post-VCO divider value in
36 * @od_bits: the size of the post-VCO divider field in bits
37 * @od_max: the maximum post-VCO divider value
38 * @od_encoding: a pointer to an array mapping post-VCO divider values to
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| /Linux-v6.1/tools/testing/selftests/tc-testing/ |
| D | README | 134 -P, --pause Pause execution just before post-suite stage
198 pre- and post-suite
199 pre- and post-case
200 pre- and post-execute stage
220 - post (post-suite)
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| /Linux-v6.1/drivers/gpu/drm/amd/amdgpu/ |
| D | amdgpu_pll.c | 75 * @post_div: post divider
81 * Calculate feedback and reference divider for a given post divider. Makes
90 /* limit reference * post divider to a maximum */ in amdgpu_pll_get_fb_ref_div()
161 /* determine allowed post divider range */ in amdgpu_pll_compute()
201 /* now search for a post divider */ in amdgpu_pll_compute()
257 DRM_DEBUG_KMS("%d - %d, pll dividers - fb: %d.%d ref: %d, post %d\n", in amdgpu_pll_compute()
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| /Linux-v6.1/Documentation/userspace-api/media/dvb/ |
| D | frontend-stat-properties.rst | 148 .. _DTV-STAT-POST-ERROR-BIT-COUNT:
162 :ref:`DTV_STAT_POST_TOTAL_BIT_COUNT <DTV-STAT-POST-TOTAL-BIT-COUNT>`.
177 .. _DTV-STAT-POST-TOTAL-BIT-COUNT:
184 :ref:`DTV_STAT_POST_ERROR_BIT_COUNT <DTV-STAT-POST-ERROR-BIT-COUNT>`
202 :ref:`DTV_STAT_POST_ERROR_BIT_COUNT <DTV-STAT-POST-ERROR-BIT-COUNT>`.
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