| /Linux-v6.1/drivers/clk/ingenic/ |
| D | jz4780-cgu.c | 294 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
300 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
306 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
312 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
322 .parents = { -1, -1, JZ4780_CLK_EXCLK, -1 },
330 .parents = { -1, JZ4780_CLK_APLL, JZ4780_CLK_EXCLK,
337 .parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,
349 .parents = { JZ4780_CLK_CPUMUX, -1, -1, -1 },
360 .parents = { JZ4780_CLK_CPUMUX, -1, -1, -1 },
366 .parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,
[all …]
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| D | jz4760-cgu.c | 96 .parents = { JZ4760_CLK_EXT },
121 .parents = { JZ4760_CLK_EXT },
151 .parents = { JZ4760_CLK_PLL0, },
159 .parents = { JZ4760_CLK_PLL0, },
167 .parents = { JZ4760_CLK_PLL0, },
175 .parents = { JZ4760_CLK_PLL0, },
184 * Disabling MCLK or its parents will render DRAM
188 .parents = { JZ4760_CLK_PLL0, },
196 .parents = { JZ4760_CLK_PLL0, },
207 .parents = { JZ4760_CLK_PLL0 },
[all …]
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| D | jz4770-cgu.c | 104 .parents = { JZ4770_CLK_EXT },
128 .parents = { JZ4770_CLK_EXT },
157 .parents = { JZ4770_CLK_PLL0, },
165 .parents = { JZ4770_CLK_PLL0, },
173 .parents = { JZ4770_CLK_PLL0, },
182 .parents = { JZ4770_CLK_PLL0, },
190 .parents = { JZ4770_CLK_PLL0, },
199 .parents = { JZ4770_CLK_PLL0, },
210 .parents = { JZ4770_CLK_PLL0, JZ4770_CLK_PLL1, },
217 .parents = { JZ4770_CLK_PLL0, JZ4770_CLK_PLL1, },
[all …]
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| D | x1830-cgu.c | 114 .parents = { X1830_CLK_EXCLK, -1, -1, -1 },
137 .parents = { X1830_CLK_EXCLK, -1, -1, -1 },
160 .parents = { X1830_CLK_EXCLK, -1, -1, -1 },
183 .parents = { X1830_CLK_EXCLK, -1, -1, -1 },
208 .parents = { X1830_CLK_EXCLK, -1, -1, -1 },
216 .parents = { -1, X1830_CLK_EXCLK, X1830_CLK_APLL, -1 },
222 .parents = { -1, X1830_CLK_SCLKA, X1830_CLK_MPLL, -1 },
229 .parents = { X1830_CLK_CPUMUX, -1, -1, -1 },
241 .parents = { X1830_CLK_CPUMUX, -1, -1, -1 },
247 .parents = { -1, X1830_CLK_SCLKA, X1830_CLK_MPLL, -1 },
[all …]
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| D | jz4725b-cgu.c | 56 .parents = { JZ4725B_CLK_EXT, -1, -1, -1 },
81 .parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
95 .parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
104 .parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
113 .parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
123 * Disabling MCLK or its parents will render DRAM
127 .parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
136 .parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
146 .parents = { JZ4725B_CLK_PLL_HALF, -1, -1, -1 },
153 .parents = { JZ4725B_CLK_EXT, JZ4725B_CLK_PLL_HALF, -1, -1 },
[all …]
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| D | x1000-cgu.c | 186 .parents = { X1000_CLK_EXCLK, -1, -1, -1 },
209 .parents = { X1000_CLK_EXCLK, -1, -1, -1 },
234 .parents = { -1, -1, X1000_CLK_EXCLK, -1 },
242 .parents = { -1, X1000_CLK_EXCLK, X1000_CLK_APLL, -1 },
248 .parents = { -1, X1000_CLK_SCLKA, X1000_CLK_MPLL, -1 },
259 .parents = { X1000_CLK_CPUMUX, -1, -1, -1 },
271 .parents = { X1000_CLK_CPUMUX, -1, -1, -1 },
277 .parents = { -1, X1000_CLK_SCLKA, X1000_CLK_MPLL, -1 },
284 .parents = { -1, X1000_CLK_SCLKA, X1000_CLK_MPLL, -1 },
290 .parents = { X1000_CLK_AHB2PMUX, -1, -1, -1 },
[all …]
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| D | jz4740-cgu.c | 71 .parents = { JZ4740_CLK_EXT, -1, -1, -1 },
96 .parents = { JZ4740_CLK_PLL, -1, -1, -1 },
110 .parents = { JZ4740_CLK_PLL, -1, -1, -1 },
119 .parents = { JZ4740_CLK_PLL, -1, -1, -1 },
128 .parents = { JZ4740_CLK_PLL, -1, -1, -1 },
138 * Disabling MCLK or its parents will render DRAM
142 .parents = { JZ4740_CLK_PLL, -1, -1, -1 },
151 .parents = { JZ4740_CLK_PLL_HALF, -1, -1, -1 },
161 .parents = { JZ4740_CLK_PLL_HALF, -1, -1, -1 },
167 .parents = { JZ4740_CLK_EXT, JZ4740_CLK_PLL_HALF, -1, -1 },
[all …]
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| /Linux-v6.1/drivers/clk/zynqmp/ |
| D | clkc.c | 24 /* Flags for parents */
67 * @num_parents: Number of parents of clock
98 u32 parents[CLK_GET_PARENTS_RESP_WORDS]; member
122 const char * const *parents,
303 * @parents: Name of this clock's parents
304 * @num_parents: Number of parents
310 const char * const *parents, in zynqmp_clk_register_fixed_factor() argument
334 parents[0], in zynqmp_clk_register_fixed_factor()
342 * zynqmp_pm_clock_get_parents() - Get the first 3 parents of clock for given id
345 * @response: Parents of the given clock
[all …]
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| D | clk-mux-zynqmp.c | 16 * prepare - clk_prepare only ensures that parents are prepared
17 * enable - clk_enable only ensures that parents are enabled
41 * Return: Parent index on success or number of parents in case of error
125 * @parents: Name of this clock's parents
126 * @num_parents: Number of parents
132 const char * const *parents, in zynqmp_clk_register_mux() argument
153 init.parent_names = parents; in zynqmp_clk_register_mux()
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| D | clk-zynqmp.h | 71 const char * const *parents,
76 const char * const *parents,
82 const char * const *parents,
87 const char * const *parents,
93 const char * const *parents,
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| D | clk-gate-zynqmp.c | 101 * @parents: Name of this clock's parents
102 * @num_parents: Number of parents
108 const char * const *parents, in zynqmp_clk_register_gate() argument
127 init.parent_names = parents; in zynqmp_clk_register_gate()
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| /Linux-v6.1/drivers/clk/st/ |
| D | clkgen-mux.c | 21 const char **parents; in clkgen_mux_get_parents() local
28 parents = kcalloc(nparents, sizeof(const char *), GFP_KERNEL); in clkgen_mux_get_parents()
29 if (!parents) in clkgen_mux_get_parents()
32 *num_parents = of_clk_parent_fill(np, parents, nparents); in clkgen_mux_get_parents()
33 return parents; in clkgen_mux_get_parents()
57 const char **parents; in st_of_clkgen_mux_setup() local
76 parents = clkgen_mux_get_parents(np, &num_parents); in st_of_clkgen_mux_setup()
77 if (IS_ERR(parents)) { in st_of_clkgen_mux_setup()
78 pr_err("%s: Failed to get parents (%ld)\n", in st_of_clkgen_mux_setup()
79 __func__, PTR_ERR(parents)); in st_of_clkgen_mux_setup()
[all …]
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| /Linux-v6.1/drivers/clk/starfive/ |
| D | clk-starfive-jh7100.h | 27 u8 parents[4]; member
34 .parents = { [0] = _parent }, \
41 .parents = { [0] = _parent }, \
48 .parents = { [0] = _parent }, \
55 .parents = { [0] = _parent }, \
62 .parents = { __VA_ARGS__ }, \
70 .parents = { __VA_ARGS__ }, \
77 .parents = { __VA_ARGS__ }, \
85 .parents = { __VA_ARGS__ }, \
92 .parents = { [0] = _parent }, \
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| D | clk-starfive-jh7100-audio.c | 117 struct clk_parent_data parents[4] = {}; in jh7100_audclk_probe() local
121 .parent_data = parents, in jh7100_audclk_probe()
129 unsigned int pidx = jh7100_audclk_data[idx].parents[i]; in jh7100_audclk_probe()
132 parents[i].hw = &priv->reg[pidx].hw; in jh7100_audclk_probe()
134 parents[i].fw_name = "audio_src"; in jh7100_audclk_probe()
136 parents[i].fw_name = "audio_12288"; in jh7100_audclk_probe()
138 parents[i].fw_name = "dom7ahb_bus"; in jh7100_audclk_probe()
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| /Linux-v6.1/drivers/clk/sunxi/ |
| D | clk-sun8i-mbus.c | 27 const char **parents; in sun8i_a23_mbus_setup() local
37 parents = kcalloc(num_parents, sizeof(*parents), GFP_KERNEL); in sun8i_a23_mbus_setup()
38 if (!parents) in sun8i_a23_mbus_setup()
60 of_clk_parent_fill(node, parents, num_parents); in sun8i_a23_mbus_setup()
77 clk = clk_register_composite(NULL, clk_name, parents, num_parents, in sun8i_a23_mbus_setup()
89 kfree(parents); /* parents is deep copied */ in sun8i_a23_mbus_setup()
107 kfree(parents); in sun8i_a23_mbus_setup()
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| D | clk-sun4i-display.c | 19 u8 parents; member
104 const char *parents[4]; in sun4i_a10_display_init() local
123 ret = of_clk_parent_fill(node, parents, data->parents); in sun4i_a10_display_init()
124 if (ret != data->parents) { in sun4i_a10_display_init()
125 pr_err("%s: Could not retrieve the parents\n", clk_name); in sun4i_a10_display_init()
158 parents, data->parents, in sun4i_a10_display_init()
224 .parents = 4,
242 .parents = 3,
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| /Linux-v6.1/drivers/clk/tegra/ |
| D | clk-bpmp.c | 23 unsigned int parents[MRQ_CLK_MAX_PARENTS]; member
35 unsigned int *parents; member
208 request.parent_id = clk->parents[index]; in tegra_bpmp_clk_set_parent()
249 if (clk->parents[i] == response.parent_id) in tegra_bpmp_clk_get_parent()
356 info->parents[i] = response.parents[i]; in tegra_bpmp_clk_get_info()
397 dev_printk(level, bpmp->dev, " parents: %u\n", info->num_parents); in tegra_bpmp_clk_info_dump()
400 dev_printk(level, bpmp->dev, " %03u\n", info->parents[i]); in tegra_bpmp_clk_info_dump()
432 "clock %u has too many parents (%u, max: %u)\n", in tegra_bpmp_probe_clocks()
491 const char **parents; in tegra_bpmp_clk_register() local
502 clk->parents = devm_kcalloc(bpmp->dev, info->num_parents, in tegra_bpmp_clk_register()
[all …]
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| /Linux-v6.1/drivers/clk/imx/ |
| D | clk.h | 141 #define imx_clk_mux(name, reg, shift, width, parents, num_parents) \ argument
142 to_clk(imx_clk_hw_mux(name, reg, shift, width, parents, num_parents))
144 #define imx_clk_mux_flags(name, reg, shift, width, parents, num_parents, flags) \ argument
145 to_clk(imx_clk_hw_mux_flags(name, reg, shift, width, parents, num_parents, flags))
147 #define imx_clk_mux2_flags(name, reg, shift, width, parents, num_parents, flags) \ argument
148 to_clk(imx_clk_hw_mux2_flags(name, reg, shift, width, parents, num_parents, flags))
156 #define imx_clk_mux_flags(name, reg, shift, width, parents, num_parents, flags) \ argument
157 to_clk(imx_clk_hw_mux_flags(name, reg, shift, width, parents, num_parents, flags))
195 #define imx_clk_hw_mux2(name, reg, shift, width, parents, num_parents) \ argument
196 imx_clk_hw_mux2_flags(name, reg, shift, width, parents, num_parents, 0)
[all …]
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| /Linux-v6.1/drivers/clk/pxa/ |
| D | clk-pxa27x.c | 109 #define PXA27X_CKEN(dev_id, con_id, parents, mult_hp, div_hp, \ argument
111 PXA_CKEN(dev_id, con_id, bit, parents, 1, 1, mult_hp, div_hp, \
117 PARENTS(pxa27x_pbus) = { "osc_13mhz", "ppll_312mhz" };
118 PARENTS(pxa27x_sbus) = { "system_bus", "system_bus" };
119 PARENTS(pxa27x_32Mhz_bus) = { "osc_32_768khz", "osc_32_768khz" };
120 PARENTS(pxa27x_lcd_bus) = { "lcd_base", "lcd_base" };
121 PARENTS(pxa27x_membus) = { "lcd_base", "lcd_base" };
123 #define PXA27X_CKEN_1RATE(dev_id, con_id, bit, parents, delay) \ argument
124 PXA_CKEN_1RATE(dev_id, con_id, bit, parents, \
126 #define PXA27X_CKEN_1RATE_AO(dev_id, con_id, bit, parents, delay) \ argument
[all …]
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| D | clk-pxa25x.c | 106 PARENTS(clk_pxa25x_memory) = { "run" };
109 PARENTS(pxa25x_pbus95) = { "ppll_95_85mhz", "ppll_95_85mhz" };
110 PARENTS(pxa25x_pbus147) = { "ppll_147_46mhz", "ppll_147_46mhz" };
111 PARENTS(pxa25x_osc3) = { "osc_3_6864mhz", "osc_3_6864mhz" };
113 #define PXA25X_CKEN(dev_id, con_id, parents, mult, div, \ argument
115 PXA_CKEN(dev_id, con_id, bit, parents, mult, div, mult, div, \
127 #define PXA25X_CKEN_1RATE(dev_id, con_id, bit, parents, delay) \ argument
128 PXA_CKEN_1RATE(dev_id, con_id, bit, parents, \
130 #define PXA25X_CKEN_1RATE_AO(dev_id, con_id, bit, parents, delay) \ argument
131 PXA_CKEN_1RATE(dev_id, con_id, bit, parents, \
[all …]
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| D | clk-pxa3xx.c | 191 PARENTS(clk_pxa3xx_ac97) = { "spll_624mhz" };
203 PARENTS(clk_pxa3xx_smemc) = { "spll_624mhz" };
213 PARENTS(pxa3xx_pbus) = { "ring_osc_60mhz", "spll_624mhz" };
214 PARENTS(pxa3xx_32Khz_bus) = { "osc_32_768khz", "osc_32_768khz" };
215 PARENTS(pxa3xx_13MHz_bus) = { "osc_13mhz", "osc_13mhz" };
216 PARENTS(pxa3xx_ac97_bus) = { "ring_osc_60mhz", "ac97" };
217 PARENTS(pxa3xx_sbus) = { "ring_osc_60mhz", "system_bus" };
218 PARENTS(pxa3xx_smemcbus) = { "ring_osc_60mhz", "smemc" };
221 #define PXA3XX_CKEN(dev_id, con_id, parents, mult_lp, div_lp, mult_hp, \ argument
223 PXA_CKEN(dev_id, con_id, bit, parents, mult_lp, div_lp, \
[all …]
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| D | clk-pxa.h | 17 #define PARENTS(name) \ macro
91 * This clock takes it source from 2 possible parents :
120 #define PXA_CKEN(_dev_id, _con_id, _name, parents, _mult_lp, _div_lp, \ argument
124 .dev_id = _dev_id, .con_id = _con_id, .parent_names = parents,\
131 #define PXA_CKEN_1RATE(dev_id, con_id, name, parents, cken_reg, \ argument
133 PXA_CKEN(dev_id, con_id, name, parents, 1, 1, 1, 1, \
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| /Linux-v6.1/Documentation/devicetree/bindings/phy/ |
| D | ti,phy-j721e-wiz.yaml | 59 assigned-clock-parents:
105 assigned-clock-parents:
112 - assigned-clock-parents
138 assigned-clock-parents:
145 - assigned-clock-parents
212 assigned-clock-parents = <&k3_clks 292 15>, <&k3_clks 292 4>;
221 assigned-clock-parents = <&k3_clks 293 13>;
228 assigned-clock-parents = <&k3_clks 293 0>;
246 assigned-clock-parents = <&k3_clks 292 11>;
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| /Linux-v6.1/drivers/gpu/drm/sun4i/ |
| D | sun8i_hdmi_phy_clk.c | 148 const char *parents[2]; in sun8i_phy_clk_create() local
150 parents[0] = __clk_get_name(phy->clk_pll0); in sun8i_phy_clk_create()
151 if (!parents[0]) in sun8i_phy_clk_create()
155 parents[1] = __clk_get_name(phy->clk_pll1); in sun8i_phy_clk_create()
156 if (!parents[1]) in sun8i_phy_clk_create()
166 init.parent_names = parents; in sun8i_phy_clk_create()
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| /Linux-v6.1/drivers/clk/ |
| D | clk-conf.c | 20 num_parents = of_count_phandle_with_args(node, "assigned-clock-parents", in __set_clk_parents()
23 pr_err("clk: invalid value of clock-parents property at %pOF\n", in __set_clk_parents()
27 rc = of_parse_phandle_with_args(node, "assigned-clock-parents", in __set_clk_parents()
124 * This function parses 'assigned-{clocks/clock-parents/clock-rates}' properties
125 * and sets any specified clock parents and rates. The @clk_supplier argument
127 * listed in its 'assigned-clocks' or 'assigned-clock-parents' properties.
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