| /Linux-v5.15/tools/perf/Documentation/ |
| D | perf-list.txt | 128 ARBITRARY PMUS
132 to PMUs. Using this typically requires looking up the specific event
135 The available PMUs and their raw parameters can be listed with
148 PER SOCKET PMUS
151 Some PMUs are not associated with a core, but with a whole CPU socket.
152 Events on these PMUs generally cannot be sampled, but only counted globally
162 bandwidth would require specifying all imc PMUs (see perf list output),
182 Other PMUs and global measurements are normally root only.
195 Some PMUs control advanced hardware tracing capabilities, such as Intel PT,
253 Events from multiple different PMUs cannot be mixed in a group, with
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| D | intel-hybrid.txt | 10 Kernel exports two new cpu pmus via sysfs:
213 warning and disable grouping, because the pmus in group are
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| D | perf-stat.txt | 62 of the same type of PMU in large systems (e.g. memory controller PMUs).
63 Multiple PMU instances are typical for uncore PMUs, so the prefix
443 Do not merge results from same PMUs.
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| /Linux-v5.15/arch/x86/events/intel/ |
| D | uncore.c | 937 struct intel_uncore_pmu *pmu = type->pmus; in uncore_type_exit()
948 kfree(type->pmus); in uncore_type_exit()
949 type->pmus = NULL; in uncore_type_exit()
967 struct intel_uncore_pmu *pmus; in uncore_type_init() local
971 pmus = kcalloc(type->num_boxes, sizeof(*pmus), GFP_KERNEL); in uncore_type_init()
972 if (!pmus) in uncore_type_init()
978 pmus[i].func_id = setid ? i : -1; in uncore_type_init()
979 pmus[i].pmu_idx = i; in uncore_type_init()
980 pmus[i].type = type; in uncore_type_init()
981 pmus[i].boxes = kzalloc(size, GFP_KERNEL); in uncore_type_init()
[all …]
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| /Linux-v5.15/Documentation/admin-guide/perf/ |
| D | qcom_l3_pmu.rst | 5 This driver supports the L3 cache PMUs found in Qualcomm Datacenter Technologies
12 options in sysfs, see /sys/devices/l3cache*. Given that these are uncore PMUs
25 Given that these are uncore PMUs the driver does not support sampling, therefore
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| D | thunderx2-pmu.rst | 6 PMUs such as the Level 3 Cache (L3C), DDR4 Memory Controller (DMC) and
21 The thunderx2_pmu driver registers per-socket perf PMUs for the DMC and
23 (CCPI2) events simultaneously. The PMUs provide a description of their
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| D | xgene-pmu.rst | 5 X-Gene SoC PMU consists of various independent system device PMUs such as
8 same model as the PMU for ARM cores. The PMUs share the same top level
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| D | hisi-pmu.rst | 5 The HiSilicon SoC chip includes various independent system device PMUs
6 such as L3 cache (L3C), Hydra Home Agent (HHA) and DDRC. These PMUs are
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| D | arm_dsu_pmu.rst | 11 cores connected to the same DSU. Like most of the other uncore PMUs, DSU
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| D | qcom_l2_pmu.rst | 10 the physical PMUs.
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| /Linux-v5.15/arch/powerpc/include/asm/ |
| D | imc-pmu.h | 110 * registers new IMC pmus. This structure will hold the
159 * Domains for IMC PMUs
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| /Linux-v5.15/tools/perf/util/ |
| D | pmu.c | 44 static LIST_HEAD(pmus);
572 /* Add all pmus in sysfs to pmu list: */
593 /* add to static LIST_HEAD(pmus): */ in pmu_read_sysfs()
615 * Uncore PMUs have a "cpumask" file under sysfs. CPU PMUs (e.g. on arm/arm64)
720 * PMUs other than CORE PMUs. in perf_pmu__find_map()
1036 list_add_tail(&pmu->list, &pmus); in pmu_lookup()
1055 list_for_each_entry(pmu, &pmus, list) { in pmu_find()
1068 list_for_each_entry(pmu, &pmus, list) in perf_pmu__find_by_type()
1083 pmu = list_prepare_entry(pmu, &pmus, list); in perf_pmu__scan()
1085 list_for_each_entry_continue(pmu, &pmus, list) in perf_pmu__scan()
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| D | evlist-hybrid.c | 70 "different hybrid PMUs!\n"); in evlist__warn_hybrid_group()
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| /Linux-v5.15/drivers/perf/ |
| D | qcom_l2_pmu.c | 107 * the hardware PMUs.
123 * This structure represents one of the hardware PMUs.
424 * physical PMUs (per cluster), because we do not support per-task mode in l2_cache_pmu_enable()
471 /* Don't allow groups with mixed PMUs, except for s/w events */ in l2_cache_event_init()
943 dev_err(&pdev->dev, "No hardware L2 cache PMUs found\n"); in l2_cache_pmu_probe()
960 dev_info(&pdev->dev, "Registered L2 cache PMU using %d HW PMUs\n", in l2_cache_pmu_probe()
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| D | qcom_l3_pmu.c | 3 * Driver for the L3 cache PMUs in Qualcomm Technologies chips.
448 * We must NOT create groups containing events from multiple hardware PMUs,
449 * although mixing different software and hardware PMUs is allowed.
510 * single CPU context. This is obvious for CPU PMUs, where one in qcom_l3_cache__event_init()
512 * but can lead to issues for off-core PMUs, like this one, where in qcom_l3_cache__event_init()
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| D | arm_pmu_acpi.c | 159 * them with their PMUs. in arm_pmu_acpi_parse_irqs()
293 * Initialise and register the set of PMUs which we know about right in arm_pmu_acpi_probe()
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| D | arm_dmc620_pmu.c | 493 * DMC 620 PMUs are shared across all cpus and cannot in dmc620_pmu_event_init()
505 * single CPU context. This is obvious for CPU PMUs, where one in dmc620_pmu_event_init()
507 * but can lead to issues for off-core PMUs, where each in dmc620_pmu_event_init()
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| /Linux-v5.15/include/linux/regulator/ |
| D | act8865.h | 3 * act8865.h -- Voltage regulation for active-semi act88xx PMUs
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| /Linux-v5.15/Documentation/powerpc/ |
| D | imc.rst | 42 Some PMUs may have a common scale and unit values for all their supported
53 `ibm,opal-in-memory-counters`. From the device tree, the kernel parses the PMUs
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| /Linux-v5.15/arch/x86/events/ |
| D | rapl.c | 118 struct rapl_pmu *pmus[]; member
150 return dieid < rapl_pmus->maxdie ? rapl_pmus->pmus[dieid] : NULL; in cpu_to_rapl_pmu()
582 rapl_pmus->pmus[topology_logical_die_id(cpu)] = pmu; in rapl_cpu_online()
667 kfree(rapl_pmus->pmus[i]); in cleanup_rapl_pmus()
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| /Linux-v5.15/Documentation/riscv/ |
| D | pmu.rst | 2 Supporting PMUs on RISC-V platforms
36 PMUs in the kernel. The following sections briefly explain perf' mechanism
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| /Linux-v5.15/Documentation/devicetree/bindings/arm/samsung/ |
| D | pmu.yaml | 70 Some PMUs are capable of behaving as an interrupt controller (mostly
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| /Linux-v5.15/drivers/perf/hisilicon/ |
| D | hisi_uncore_pmu.h | 9 * This code is based on the uncore PMUs like arm-cci and arm-ccn.
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| D | hisi_uncore_sllc_pmu.c | 8 * This code is based on the uncore PMUs like arm-cci and arm-ccn.
307 /* SLLC PMUs only share the same SCCL */ in hisi_sllc_pmu_init_data()
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| D | hisi_uncore_ddrc_pmu.c | 9 * This code is based on the uncore PMUs like arm-cci and arm-ccn.
315 /* DDRC PMUs only share the same SCCL */ in hisi_ddrc_pmu_init_data()
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