| /Linux-v6.1/drivers/clk/baikal-t1/ |
| D | clk-ccu-pll.c | 57 * Alas we have to mark all PLLs as critical. CPU and DDR PLLs are sources of
59 * shouldn't be ever gated. SATA and PCIe PLLs are the parents of APB-bus and
61 * unusable. Moreover disabling SATA and Ethernet PLLs causes automatic reset
63 * all the devices consuming those PLLs, they will be marked as critical too.
81 struct ccu_pll *plls[CCU_PLL_NUM]; member
93 return data->plls[idx]; in ccu_pll_find_desc()
156 /* Defer non-basic PLLs allocation for the probe stage */ in ccu_pll_clk_register()
158 if (!data->plls[idx]) in ccu_pll_clk_register()
159 data->plls[idx] = ERR_PTR(-EPROBE_DEFER); in ccu_pll_clk_register()
173 data->plls[idx] = ccu_pll_hw_register(&init); in ccu_pll_clk_register()
[all …]
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| D | Kconfig | 11 in them are fed with clocks generated by a hierarchy of PLLs,
13 to select Baikal-T1 CCU PLLs and Dividers drivers.
18 bool "Baikal-T1 CCU PLLs support"
22 Enable this to support the PLLs embedded into the Baikal-T1 SoC
23 System Controller. These are five PLLs placed at the root of the
36 between AXI-bus and system devices coming from CCU PLLs of Baikal-T1
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| /Linux-v6.1/Documentation/devicetree/bindings/clock/ |
| D | baikal,bt1-ccu-pll.yaml | 19 by means of PLLs and gateable/non-gateable dividers embedded into the CCU.
22 in general can provide any frequency supported by the CCU PLLs).
23 2) PLLs clocks generators (PLLs) - described in this binding file.
31 | +-|PLLs|------|- DDR controller
47 output is primarily connected to a set of CCU PLLs. There are five PLLs
51 peripherals. Each of the PLLs is based on True Circuits TSMC CLN28HPM core
53 the PLL configuration procedure. The PLLs work as depicted on the next
77 The PLLs CLKOUT is then either directly connected with the corresponding
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| D | baikal,bt1-ccu-div.yaml | 19 by means of an embedded into CCU PLLs and gateable/non-gateable dividers. The
24 in general can provide any frequency supported by the CCU PLLs).
25 2) PLLs clocks generators (PLLs).
34 | +-|PLLs|------|- DDR controller
50 output is primarily connected to a set of CCU PLLs. Some of PLLs CLKOUT are
66 where CLKIN is the reference clock coming either from CCU PLLs or from an
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| D | brcm,bcm2835-cprman.txt | 7 of the BCM2835. There is a level of PLLs deriving from an external
9 few PLLs, and a level of mostly-generic clock generators sourcing from
|
| D | st,nomadik.txt | 7 PLLs and clock gates.
23 PLL nodes: these nodes represent the two PLLs on the system,
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| /Linux-v6.1/drivers/clk/bcm/ |
| D | clk-iproc.h | 36 * Some PLLs require the PLL SW override bit to be set before changes can be
42 * Some PLLs use a different way to control clock power, via the PWRDWN bit in
48 * Some PLLs have separate registers for Status and Control. Identify this to
54 * Some PLLs have an additional divide by 2 in master clock calculation;
61 * Some PLLs provide a look up table for the leaf clock frequencies and
69 * Some PLLs have an active low reset
181 * Main clock control parameters for clocks derived from the PLLs
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| /Linux-v6.1/drivers/clk/mediatek/ |
| D | clk-mt8186-apmixedsys.c | 44 static const struct mtk_pll_data plls[] = { variable
94 r = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); in clk_mt8186_apmixed_probe()
107 mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data); in clk_mt8186_apmixed_probe()
119 mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data); in clk_mt8186_apmixed_remove()
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| D | clk-mt6795-apmixedsys.c | 44 static const struct mtk_pll_data plls[] = { variable
100 ret = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); in clk_mt6795_apmixed_probe()
127 mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data); in clk_mt6795_apmixed_probe()
140 mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data); in clk_mt6795_apmixed_remove()
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| D | clk-mt8195-apmixedsys.c | 59 static const struct mtk_pll_data plls[] = { variable
123 r = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); in clk_mt8195_apmixed_probe()
142 mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data); in clk_mt8195_apmixed_probe()
155 mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data); in clk_mt8195_apmixed_remove()
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| D | clk-mt7986-apmixed.c | 44 static const struct mtk_pll_data plls[] = { variable
74 clk_data = mtk_alloc_clk_data(ARRAY_SIZE(plls)); in clk_mt7986_apmixed_probe()
78 mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); in clk_mt7986_apmixed_probe()
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| D | clk-pll.h | 52 const struct mtk_pll_data *plls, int num_plls,
54 void mtk_clk_unregister_plls(const struct mtk_pll_data *plls, int num_plls,
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| D | clk-pll.c | 36 * MediaTek PLLs are configured through their pcw value. The pcw value describes
377 const struct mtk_pll_data *plls, int num_plls, in mtk_clk_register_plls() argument
391 const struct mtk_pll_data *pll = &plls[i]; in mtk_clk_register_plls()
414 const struct mtk_pll_data *pll = &plls[i]; in mtk_clk_register_plls()
434 void mtk_clk_unregister_plls(const struct mtk_pll_data *plls, int num_plls, in mtk_clk_unregister_plls() argument
444 const struct mtk_pll_data *pll = &plls[i - 1]; in mtk_clk_unregister_plls()
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| /Linux-v6.1/drivers/gpu/drm/omapdrm/dss/ |
| D | pll.c | 32 for (i = 0; i < ARRAY_SIZE(dss->plls); ++i) { in dss_pll_register()
33 if (!dss->plls[i]) { in dss_pll_register()
34 dss->plls[i] = pll; in dss_pll_register()
48 for (i = 0; i < ARRAY_SIZE(dss->plls); ++i) { in dss_pll_unregister()
49 if (dss->plls[i] == pll) { in dss_pll_unregister()
50 dss->plls[i] = NULL; in dss_pll_unregister()
61 for (i = 0; i < ARRAY_SIZE(dss->plls); ++i) { in dss_pll_find()
62 if (dss->plls[i] && strcmp(dss->plls[i]->name, name) == 0) in dss_pll_find()
63 return dss->plls[i]; in dss_pll_find()
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| /Linux-v6.1/arch/arm/mach-ep93xx/ |
| D | hardware.h | 14 * loops (PLLs) to multiply the incoming external clock signal to much
16 * to produce the needed clocks. The PLLs operate independently of one
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| /Linux-v6.1/drivers/clk/ |
| D | clk-k210.c | 282 * PLLs.
301 * PLLs configuration: by default PLL0 runs at 780 MHz and PLL1 at 299 MHz.
326 * @plls: SoC PLLs descriptors
333 struct k210_pll plls[K210_PLL_NUM]; member
549 struct k210_pll *pll = &ksc->plls[pllid]; in k210_register_pll()
553 { .hw = &ksc->plls[K210_PLL0].hw }, in k210_register_pll()
554 { .hw = &ksc->plls[K210_PLL1].hw }, in k210_register_pll()
574 k210_init_pll(ksc->regs, i, &ksc->plls[i]); in k210_register_plls()
652 { .hw = &ksc->plls[K210_PLL0].hw }, in k210_register_aclk()
826 { .hw = &ksc->plls[K210_PLL0].hw } in k210_register_mux_clk()
[all …]
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| D | Kconfig | 51 This driver supports the HSDK core, system, ddr, tunnel and hdmi PLLs
60 Low-Noise JESD204B Compliant Clock Jitter Cleaner With Dual Loop PLLs
196 synthesizer. Each chip has different number of PLLs and outputs.
197 For example, the CDCE925 contains two PLLs with spread-spectrum
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| /Linux-v6.1/Documentation/devicetree/bindings/arm/mediatek/ |
| D | mediatek,mt8186-sys-clock.yaml | 14 PLLs -->
20 The apmixedsys provides most of PLLs which generated from SoC 26m.
|
| D | mediatek,mt8195-sys-clock.yaml | 14 PLLs -->
20 The apmixedsys provides most of PLLs which generated from SoC 26m.
|
| /Linux-v6.1/sound/soc/uniphier/ |
| D | aio-cpu.c | 32 return chip->plls[pll_id].enable; in is_valid_pll()
138 pll = &aio->chip->plls[pll_id]; in find_divider()
658 chip->plls = devm_kcalloc(dev, in uniphier_aio_probe()
662 if (!chip->plls) in uniphier_aio_probe()
664 memcpy(chip->plls, chip->chip_spec->plls, in uniphier_aio_probe()
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| /Linux-v6.1/drivers/clk/samsung/ |
| D | clk-s3c2410.c | 33 /* list of PLLs to be registered */
348 /* Register PLLs. */ in s3c2410_common_clk_init()
355 * plls follow different calculation schemes, with the in s3c2410_common_clk_init()
356 * upll following the same scheme as the s3c2410 plls in s3c2410_common_clk_init()
364 /* Register PLLs. */ in s3c2410_common_clk_init()
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| /Linux-v6.1/drivers/cpufreq/ |
| D | s3c24xx-cpufreq.c | 620 * @plls: The list of PLL entries.
621 * @plls_no: The size of the PLL entries @plls.
623 * Register the given set of PLLs with the system.
625 int s3c_plltab_register(struct cpufreq_frequency_table *plls, in s3c_plltab_register() argument
635 memcpy(vals, plls, size); in s3c_plltab_register()
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| /Linux-v6.1/drivers/clk/sunxi-ng/ |
| D | ccu_sdm.c | 80 * some PLLs support this. On later SoCs, all PLLs support this.
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| /Linux-v6.1/arch/arm/mach-tegra/ |
| D | sleep-tegra20.S | 275 * In LP0 and LP1 all PLLs will be turned off. Switch the CPU and system clock
280 * start by switching to CLKM to safely disable PLLs, then switch to
290 /* 2uS delay delay between changing SCLK and disabling PLLs */
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| /Linux-v6.1/include/dt-bindings/clock/ |
| D | oxsemi,ox820.h | 9 /* PLLs */
|
