Home
last modified time | relevance | path

Searched +full:pl +full:- +full:sysmon (Results 1 – 5 of 5) sorted by relevance

/Linux-v6.6/Documentation/devicetree/bindings/iio/adc/
Dxlnx,zynqmp-ams.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/xlnx,zynqmp-ams.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Anand Ashok Dumbre <anand.ashok.dumbre@xilinx.com>
13 The AMS (Analog Monitoring System) includes an ADC as well as on-chip sensors
14 that can be used to sample external voltages and monitor on-die operating
16 The AMS has two SYSMON blocks which are PL (Programmable Logic) SYSMON and
17 PS (Processing System) SYSMON.
18 All designs should have AMS registers, but PS and PL are optional. The
[all …]
/Linux-v6.6/drivers/iio/adc/
Dxilinx-ams.c1 // SPDX-License-Identifier: GPL-2.0
15 #include <linux/devm-helpers.h>
123 #define AMS_ALARM_THR_MAX (BIT(16) - 1)
164 #define AMS_TEMP_OFFSET -((280230LL << 16) / 509314)
263 * struct ams - This structure contains necessary state for xilinx-ams to operate
266 * @pl_base: physical base address of PL device
274 * @ams_unmask_work: re-enables event once the event condition disappears
296 val = readl(ams->ps_base + offset); in ams_ps_update_reg()
298 writel(regval, ams->ps_base + offset); in ams_ps_update_reg()
306 val = readl(ams->pl_base + offset); in ams_pl_update_reg()
[all …]
/Linux-v6.6/arch/arm64/boot/dts/xilinx/
Dzynqmp-zcu111-revA.dts1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2017 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 /dts-v1/;
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/input/input.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
18 #include <dt-bindings/phy/phy.h>
22 compatible = "xlnx,zynqmp-zcu111-revA", "xlnx,zynqmp-zcu111", "xlnx,zynqmp";
[all …]
Dzynqmp-zcu106-revA.dts1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2016 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 /dts-v1/;
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/input/input.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
18 #include <dt-bindings/phy/phy.h>
22 compatible = "xlnx,zynqmp-zcu106-revA", "xlnx,zynqmp-zcu106", "xlnx,zynqmp";
[all …]
Dzynqmp-zcu102-revA.dts1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2015 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 /dts-v1/;
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/input/input.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
18 #include <dt-bindings/phy/phy.h>
22 compatible = "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
[all …]