| /Linux-v5.15/drivers/pinctrl/ |
| D | pinctrl-single.c | 210 #define PCS_QUIRK_HAS_SHARED_IRQ (pcs->flags & PCS_QUIRK_SHARED_IRQ)
211 #define PCS_HAS_IRQ (pcs->flags & PCS_FEAT_IRQ)
212 #define PCS_HAS_PINCONF (pcs->flags & PCS_FEAT_PINCONF)
273 static unsigned int pcs_pin_reg_offset_get(struct pcs_device *pcs, in pcs_pin_reg_offset_get() argument
276 unsigned int mux_bytes = pcs->width / BITS_PER_BYTE; in pcs_pin_reg_offset_get()
278 if (pcs->bits_per_mux) { in pcs_pin_reg_offset_get()
281 pin_offset_bytes = (pcs->bits_per_pin * pin) / BITS_PER_BYTE; in pcs_pin_reg_offset_get()
288 static unsigned int pcs_pin_shift_reg_get(struct pcs_device *pcs, in pcs_pin_shift_reg_get() argument
291 return (pin % (pcs->width / pcs->bits_per_pin)) * pcs->bits_per_pin; in pcs_pin_shift_reg_get()
298 struct pcs_device *pcs; in pcs_pin_dbg_show() local
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| /Linux-v5.15/drivers/net/ethernet/stmicro/stmmac/ |
| D | altr_tse_pcs.c | 66 static int tse_pcs_reset(void __iomem *base, struct tse_pcs *pcs) in tse_pcs_reset() argument
84 dev_err(pcs->dev, "PCS could not get out of sw reset\n"); in tse_pcs_reset()
91 int tse_pcs_init(void __iomem *base, struct tse_pcs *pcs) in tse_pcs_init() argument
102 ret = tse_pcs_reset(base, pcs); in tse_pcs_init()
105 pcs->sgmii_adapter_base + SGMII_ADAPTER_CTRL_REG); in tse_pcs_init()
110 static void pcs_link_timer_callback(struct tse_pcs *pcs) in pcs_link_timer_callback() argument
113 void __iomem *tse_pcs_base = pcs->tse_pcs_base; in pcs_link_timer_callback()
114 void __iomem *sgmii_adapter_base = pcs->sgmii_adapter_base; in pcs_link_timer_callback()
120 dev_dbg(pcs->dev, "Adapter: Link is established\n"); in pcs_link_timer_callback()
124 mod_timer(&pcs->aneg_link_timer, jiffies + in pcs_link_timer_callback()
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| D | dwmac-socfpga.c | 57 struct tse_pcs pcs; member
65 void __iomem *tse_pcs_base = dwmac->pcs.tse_pcs_base; in socfpga_dwmac_fix_mac_speed()
66 void __iomem *sgmii_adapter_base = dwmac->pcs.sgmii_adapter_base; in socfpga_dwmac_fix_mac_speed()
97 tse_pcs_fix_mac_speed(&dwmac->pcs, phy_dev, speed); in socfpga_dwmac_fix_mac_speed()
187 dwmac->pcs.sgmii_adapter_base = in socfpga_dwmac_parse_data()
190 if (IS_ERR(dwmac->pcs.sgmii_adapter_base)) { in socfpga_dwmac_parse_data()
191 ret = PTR_ERR(dwmac->pcs.sgmii_adapter_base); in socfpga_dwmac_parse_data()
209 dwmac->pcs.tse_pcs_base = in socfpga_dwmac_parse_data()
212 if (IS_ERR(dwmac->pcs.tse_pcs_base)) { in socfpga_dwmac_parse_data()
213 ret = PTR_ERR(dwmac->pcs.tse_pcs_base); in socfpga_dwmac_parse_data()
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| D | common.h | 18 #include <linux/pcs/pcs-xpcs.h>
161 /* PCS */
237 /* PCS defines */
252 #define DMA_HW_FEAT_PCSSEL 0x00000040 /* PCS registers */
279 /* PCS status and mask defines */
280 #define PCS_ANE_IRQ BIT(2) /* PCS Auto-Negotiation */
281 #define PCS_LINK_IRQ BIT(1) /* PCS Link */
380 unsigned int pcs; member
527 unsigned int pcs; member
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| D | altr_tse_pcs.h | 21 int tse_pcs_init(void __iomem *base, struct tse_pcs *pcs);
22 void tse_pcs_fix_mac_speed(struct tse_pcs *pcs, struct phy_device *phy_dev,
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| /Linux-v5.15/drivers/net/pcs/ |
| D | pcs-lynx.c | 3 * Lynx PCS MDIO helpers
8 #include <linux/pcs-lynx.h>
10 #define SGMII_CLOCK_PERIOD_NS 8 /* PCS is clocked at 125 MHz */
32 #define phylink_pcs_to_lynx(pl_pcs) container_of((pl_pcs), struct lynx_pcs, pcs)
34 static void lynx_pcs_get_state_usxgmii(struct mdio_device *pcs, in lynx_pcs_get_state_usxgmii() argument
37 struct mii_bus *bus = pcs->bus; in lynx_pcs_get_state_usxgmii()
38 int addr = pcs->addr; in lynx_pcs_get_state_usxgmii()
57 static void lynx_pcs_get_state_2500basex(struct mdio_device *pcs, in lynx_pcs_get_state_2500basex() argument
60 struct mii_bus *bus = pcs->bus; in lynx_pcs_get_state_2500basex()
61 int addr = pcs->addr; in lynx_pcs_get_state_2500basex()
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| D | Makefile | 2 # Makefile for Linux PCS drivers
4 pcs_xpcs-$(CONFIG_PCS_XPCS) := pcs-xpcs.o pcs-xpcs-nxp.o
7 obj-$(CONFIG_PCS_LYNX) += pcs-lynx.o
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| D | pcs-xpcs-nxp.c | 4 #include <linux/pcs/pcs-xpcs.h>
5 #include "pcs-xpcs.h"
67 /* In NXP SJA1105, the PCS is integrated with a PMA that has the TX lane
70 * PCS, via the DIGITAL_CONTROL_2 register.
126 /* Select PCS as transmitter data source. */ in nxp_sja1110_pma_config()
153 * Release reset of PMA to enable data flow to/from PCS. in nxp_sja1110_pma_config()
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| D | Kconfig | 3 # PCS Layer Configuration
6 menu "PCS device drivers"
18 This module provides helpers to phylink for managing the Lynx PCS
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| D | pcs-xpcs.c | 10 #include <linux/pcs/pcs-xpcs.h>
14 #include "pcs-xpcs.h"
17 container_of((pl_pcs), struct dw_xpcs, pcs)
833 static int xpcs_config(struct phylink_pcs *pcs, unsigned int mode, in xpcs_config() argument
838 struct dw_xpcs *xpcs = phylink_pcs_to_xpcs(pcs); in xpcs_config()
918 static void xpcs_get_state(struct phylink_pcs *pcs, in xpcs_get_state() argument
921 struct dw_xpcs *xpcs = phylink_pcs_to_xpcs(pcs); in xpcs_get_state()
980 void xpcs_link_up(struct phylink_pcs *pcs, unsigned int mode, in xpcs_link_up() argument
983 struct dw_xpcs *xpcs = phylink_pcs_to_xpcs(pcs); in xpcs_link_up()
997 /* First, search C73 PCS using PCS MMD */ in xpcs_get_id()
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| /Linux-v5.15/include/linux/ |
| D | phylink.h | 64 * @pcs_poll: MAC PCS cannot provide link change interrupt
67 * @ovr_an_inband: if true, override PCS to MLO_AN_INBAND
150 * Read the current inband link state from the MAC PCS, reporting the
197 * where the PCS and MAC are not tightly integrated.)
203 * the results of in-band negotiation/status from the MAC PCS should be used
267 * complete any necessary steps after the MAC and PCS have been configured
312 * where these settings are not automatically conveyed from the PCS block,
333 * struct phylink_pcs - PHYLINK PCS instance
335 * @poll: poll the PCS for link changes
337 * This structure is designed to be embedded within the PCS private data,
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| D | pcs-lynx.h | 3 * Lynx PCS helpers
13 struct phylink_pcs pcs; member
19 void lynx_pcs_destroy(struct lynx_pcs *pcs);
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| /Linux-v5.15/drivers/gpu/drm/amd/amdgpu/ |
| D | amdgpu_xgmi.c | 98 {"XGMI PCS DataLossErr",
100 {"XGMI PCS TrainingErr",
102 {"XGMI PCS CRCErr",
104 {"XGMI PCS BERExceededErr",
106 {"XGMI PCS TxMetaDataErr",
108 {"XGMI PCS ReplayBufParityErr",
110 {"XGMI PCS DataParityErr",
112 {"XGMI PCS ReplayFifoOverflowErr",
114 {"XGMI PCS ReplayFifoUnderflowErr",
116 {"XGMI PCS ElasticFifoOverflowErr",
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| /Linux-v5.15/drivers/clocksource/ |
| D | timer-pistachio.c | 73 struct pistachio_clocksource *pcs = to_pistachio_clocksource(cs); in pistachio_clocksource_read_cycles() local
82 raw_spin_lock_irqsave(&pcs->lock, flags); in pistachio_clocksource_read_cycles()
83 overflow = gpt_readl(pcs->base, TIMER_CURRENT_OVERFLOW_VALUE, 0); in pistachio_clocksource_read_cycles()
84 counter = gpt_readl(pcs->base, TIMER_CURRENT_VALUE, 0); in pistachio_clocksource_read_cycles()
85 raw_spin_unlock_irqrestore(&pcs->lock, flags); in pistachio_clocksource_read_cycles()
98 struct pistachio_clocksource *pcs = to_pistachio_clocksource(cs); in pistachio_clksrc_set_mode() local
101 val = gpt_readl(pcs->base, TIMER_CFG, timeridx); in pistachio_clksrc_set_mode()
107 gpt_writel(pcs->base, val, TIMER_CFG, timeridx); in pistachio_clksrc_set_mode()
112 struct pistachio_clocksource *pcs = to_pistachio_clocksource(cs); in pistachio_clksrc_enable() local
116 gpt_writel(pcs->base, RELOAD_VALUE, TIMER_RELOAD_VALUE, timeridx); in pistachio_clksrc_enable()
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| /Linux-v5.15/drivers/net/ethernet/freescale/dpaa2/ |
| D | dpaa2-mac.c | 98 * pcs-lynx in dpaa2_mac_phy_mode_mismatch()
102 if (mac->pcs && in dpaa2_mac_phy_mode_mismatch()
259 node = fwnode_find_reference(dpmac_node, "pcs-handle", 0); in dpaa2_pcs_create()
262 netdev_warn(mac->net_dev, "pcs-handle node not found\n"); in dpaa2_pcs_create()
267 netdev_err(mac->net_dev, "pcs-handle node not available\n"); in dpaa2_pcs_create()
277 mac->pcs = lynx_pcs_create(mdiodev); in dpaa2_pcs_create()
278 if (!mac->pcs) { in dpaa2_pcs_create()
289 struct lynx_pcs *pcs = mac->pcs; in dpaa2_pcs_destroy() local
291 if (pcs) { in dpaa2_pcs_destroy()
292 struct device *dev = &pcs->mdio->dev; in dpaa2_pcs_destroy()
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| /Linux-v5.15/arch/arm64/boot/dts/freescale/ |
| D | fsl-ls1088a-rdb.dts | 23 pcs-handle = <&pcs2>;
30 pcs-handle = <&pcs3_0>;
37 pcs-handle = <&pcs3_1>;
44 pcs-handle = <&pcs3_2>;
51 pcs-handle = <&pcs3_3>;
58 pcs-handle = <&pcs7_0>;
65 pcs-handle = <&pcs7_1>;
72 pcs-handle = <&pcs7_2>;
79 pcs-handle = <&pcs7_3>;
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| D | fsl-ls1088a-ten64.dts | 97 pcs-handle = <&pcs1>;
105 pcs-handle = <&pcs2>;
115 pcs-handle = <&pcs3_0>;
122 pcs-handle = <&pcs3_1>;
129 pcs-handle = <&pcs3_2>;
136 pcs-handle = <&pcs3_3>;
144 pcs-handle = <&pcs7_0>;
151 pcs-handle = <&pcs7_1>;
158 pcs-handle = <&pcs7_2>;
165 pcs-handle = <&pcs7_3>;
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| /Linux-v5.15/drivers/net/ethernet/microchip/sparx5/ |
| D | sparx5_phylink.c | 140 static struct sparx5_port *sparx5_pcs_to_port(struct phylink_pcs *pcs) in sparx5_pcs_to_port() argument
142 return container_of(pcs, struct sparx5_port, phylink_pcs); in sparx5_pcs_to_port()
145 static void sparx5_pcs_get_state(struct phylink_pcs *pcs, in sparx5_pcs_get_state() argument
148 struct sparx5_port *port = sparx5_pcs_to_port(pcs); in sparx5_pcs_get_state()
159 static int sparx5_pcs_config(struct phylink_pcs *pcs, in sparx5_pcs_config() argument
165 struct sparx5_port *port = sparx5_pcs_to_port(pcs); in sparx5_pcs_config()
187 /* Enable the PCS matching this interface type */ in sparx5_pcs_config()
190 netdev_err(port->ndev, "port PCS config failed: %d\n", ret); in sparx5_pcs_config()
194 static void sparx5_pcs_aneg_restart(struct phylink_pcs *pcs) in sparx5_pcs_aneg_restart() argument
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| D | sparx5_port.c | 85 /* Get PCS Link down sticky */ in sparx5_get_dev2g5_status()
103 /* Get PCS ANEG status register */ in sparx5_get_dev2g5_status()
327 /* 1: Reset the PCS Rx clock domain */ in sparx5_port_disable()
339 /* 1: Reset the PCS Rx clock domain */ in sparx5_port_disable()
429 u32 pcs = sparx5_to_pcs_dev(port->portno); in sparx5_port_disable() local
430 void __iomem *pcsinst = spx5_inst_get(sparx5, pcs, tinst); in sparx5_port_disable()
432 /* 12: Disable 5G/10G/25 BaseR PCS */ in sparx5_port_disable()
439 /* Disable 25G PCS */ in sparx5_port_disable()
445 /* 12: Disable 1G PCS */ in sparx5_port_disable()
748 /* Choose SGMII or 1000BaseX/2500BaseX PCS mode */ in sparx5_port_pcs_low_set()
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| /Linux-v5.15/drivers/net/phy/ |
| D | phylink.c | 48 struct phylink_pcs *pcs; member
388 /* Check if MAC/PCS also supports Autoneg. */ in phylink_parse_mode()
444 pl->pcs_ops->pcs_an_restart(pl->pcs); in phylink_mac_pcs_an_restart()
470 err = pl->pcs_ops->pcs_config(pl->pcs, pl->cur_link_an_mode, in phylink_major_config()
495 * If we have a separate PCS, we only need to call its pcs_config() method,
519 /* Modern PCS-based method; update the advert at the PCS, and in phylink_change_inband_advert()
523 ret = pl->pcs_ops->pcs_config(pl->pcs, pl->cur_link_an_mode, in phylink_change_inband_advert()
550 pl->pcs_ops->pcs_get_state(pl->pcs, state); in phylink_mac_pcs_get_state()
623 pl->pcs_ops->pcs_link_up(pl->pcs, pl->cur_link_an_mode, in phylink_link_up()
724 * old mac_config() method to configure the MAC/PCS in phylink_resolve()
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| /Linux-v5.15/arch/mips/cavium-octeon/executive/ |
| D | cvmx-helper-sgmii.c | 65 * Write PCS*_LINK*_TIMER_COUNT_REG[COUNT] with the in __cvmx_helper_sgmii_hardware_init_one_time()
88 * 1000BASE-X mode, tx_Config_Reg<D15:D0> is PCS*_AN*_ADV_REG. in __cvmx_helper_sgmii_hardware_init_one_time()
90 * PCS*_SGM*_AN_ADV_REG. In SGMII MAC mode, in __cvmx_helper_sgmii_hardware_init_one_time()
142 * Take PCS through a reset sequence. in __cvmx_helper_sgmii_hardware_init_link()
143 * PCS*_MR*_CONTROL_REG[PWR_DN] should be cleared to zero. in __cvmx_helper_sgmii_hardware_init_link()
144 * Write PCS*_MR*_CONTROL_REG[RESET]=1 (while not changing the in __cvmx_helper_sgmii_hardware_init_link()
145 * value of the other PCS*_MR*_CONTROL_REG bits). Read in __cvmx_helper_sgmii_hardware_init_link()
146 * PCS*_MR*_CONTROL_REG[RESET] until it changes value to in __cvmx_helper_sgmii_hardware_init_link()
166 * Write PCS*_MR*_CONTROL_REG[RST_AN]=1 to ensure a fresh in __cvmx_helper_sgmii_hardware_init_link()
176 * Wait for PCS*_MR*_STATUS_REG[AN_CPT] to be set, indicating in __cvmx_helper_sgmii_hardware_init_link()
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| /Linux-v5.15/drivers/net/fddi/skfp/ |
| D | pcmplc.c | 1849 struct pcm_state *pcs ; in pcm_get_state() local
1856 for (i = 0, phy = smc->y, pcs = state->pcm_state ; i < NUMPHYS ; in pcm_get_state()
1857 i++ , phy++, pcs++ ) { in pcm_get_state()
1859 pcs->pcm_type = (u_char) mib->fddiPORTMy_Type ; in pcm_get_state()
1860 pcs->pcm_state = (u_char) mib->fddiPORTPCMState ; in pcm_get_state()
1861 pcs->pcm_mode = phy->pc_mode ; in pcm_get_state()
1862 pcs->pcm_neighbor = (u_char) mib->fddiPORTNeighborType ; in pcm_get_state()
1863 pcs->pcm_bsf = mib->fddiPORTBS_Flag ; in pcm_get_state()
1864 pcs->pcm_lsf = phy->ls_flag ; in pcm_get_state()
1865 pcs->pcm_lct_fail = (u_char) mib->fddiPORTLCTFail_Ct ; in pcm_get_state()
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| /Linux-v5.15/drivers/phy/qualcomm/ |
| D | phy-qcom-qmp.c | 123 /* PCS registers */
2773 /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
2845 /* true, if PCS block has no separate SW_RESET register */
2862 * @pcs: iomapped memory space for lane's pcs
2878 void __iomem *pcs; member
4079 qphy->pcs + QSERDES_DP_PHY_PD_CTL); in qcom_qmp_v3_phy_dp_aux_init()
4086 writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL); in qcom_qmp_v3_phy_dp_aux_init()
4092 qphy->pcs + QSERDES_DP_PHY_PD_CTL); in qcom_qmp_v3_phy_dp_aux_init()
4100 writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0); in qcom_qmp_v3_phy_dp_aux_init()
4101 writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1); in qcom_qmp_v3_phy_dp_aux_init()
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| /Linux-v5.15/Documentation/devicetree/bindings/net/ |
| D | fsl,qoriq-mc-dpmac.yaml | 33 pcs-handle:
36 A reference to a node representing a PCS PHY device found on
58 pcs-handle = <&pcs3_1>;
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| /Linux-v5.15/Documentation/networking/device_drivers/ethernet/freescale/dpaa2/ |
| D | mac-phy-support.rst | 54 | MC firmware polling MAC PCS for link |
56 | | PCS | | PCS | | PCS | | PCS | |
65 the MC firmware by polling the MAC PCS. Without the need to register a
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