| /Linux-v5.10/drivers/pinctrl/ |
| D | pinctrl-single.c | 210 #define PCS_QUIRK_HAS_SHARED_IRQ (pcs->flags & PCS_QUIRK_SHARED_IRQ)
211 #define PCS_HAS_IRQ (pcs->flags & PCS_FEAT_IRQ)
212 #define PCS_HAS_PINCONF (pcs->flags & PCS_FEAT_PINCONF)
277 struct pcs_device *pcs; in pcs_pin_dbg_show() local
282 pcs = pinctrl_dev_get_drvdata(pctldev); in pcs_pin_dbg_show()
284 mux_bytes = pcs->width / BITS_PER_BYTE; in pcs_pin_dbg_show()
286 val = pcs->read(pcs->base + offset); in pcs_pin_dbg_show()
287 pa = pcs->res->start + offset; in pcs_pin_dbg_show()
295 struct pcs_device *pcs; in pcs_dt_free_map() local
297 pcs = pinctrl_dev_get_drvdata(pctldev); in pcs_dt_free_map()
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| /Linux-v5.10/drivers/net/ethernet/stmicro/stmmac/ |
| D | altr_tse_pcs.c | 66 static int tse_pcs_reset(void __iomem *base, struct tse_pcs *pcs) in tse_pcs_reset() argument
84 dev_err(pcs->dev, "PCS could not get out of sw reset\n"); in tse_pcs_reset()
91 int tse_pcs_init(void __iomem *base, struct tse_pcs *pcs) in tse_pcs_init() argument
102 ret = tse_pcs_reset(base, pcs); in tse_pcs_init()
105 pcs->sgmii_adapter_base + SGMII_ADAPTER_CTRL_REG); in tse_pcs_init()
110 static void pcs_link_timer_callback(struct tse_pcs *pcs) in pcs_link_timer_callback() argument
113 void __iomem *tse_pcs_base = pcs->tse_pcs_base; in pcs_link_timer_callback()
114 void __iomem *sgmii_adapter_base = pcs->sgmii_adapter_base; in pcs_link_timer_callback()
120 dev_dbg(pcs->dev, "Adapter: Link is established\n"); in pcs_link_timer_callback()
124 mod_timer(&pcs->aneg_link_timer, jiffies + in pcs_link_timer_callback()
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| D | dwmac-socfpga.c | 57 struct tse_pcs pcs; member
65 void __iomem *tse_pcs_base = dwmac->pcs.tse_pcs_base; in socfpga_dwmac_fix_mac_speed()
66 void __iomem *sgmii_adapter_base = dwmac->pcs.sgmii_adapter_base; in socfpga_dwmac_fix_mac_speed()
97 tse_pcs_fix_mac_speed(&dwmac->pcs, phy_dev, speed); in socfpga_dwmac_fix_mac_speed()
187 dwmac->pcs.sgmii_adapter_base = in socfpga_dwmac_parse_data()
190 if (IS_ERR(dwmac->pcs.sgmii_adapter_base)) { in socfpga_dwmac_parse_data()
191 ret = PTR_ERR(dwmac->pcs.sgmii_adapter_base); in socfpga_dwmac_parse_data()
209 dwmac->pcs.tse_pcs_base = in socfpga_dwmac_parse_data()
212 if (IS_ERR(dwmac->pcs.tse_pcs_base)) { in socfpga_dwmac_parse_data()
213 ret = PTR_ERR(dwmac->pcs.tse_pcs_base); in socfpga_dwmac_parse_data()
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| D | common.h | 18 #include <linux/pcs/pcs-xpcs.h>
150 /* PCS */
217 /* PCS defines */
232 #define DMA_HW_FEAT_PCSSEL 0x00000040 /* PCS registers */
256 /* PCS status and mask defines */
257 #define PCS_ANE_IRQ BIT(2) /* PCS Auto-Negotiation */
258 #define PCS_LINK_IRQ BIT(1) /* PCS Link */
332 unsigned int pcs; member
477 unsigned int pcs; member
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| D | altr_tse_pcs.h | 21 int tse_pcs_init(void __iomem *base, struct tse_pcs *pcs);
22 void tse_pcs_fix_mac_speed(struct tse_pcs *pcs, struct phy_device *phy_dev,
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| /Linux-v5.10/drivers/net/pcs/ |
| D | pcs-lynx.c | 3 * Lynx PCS MDIO helpers
8 #include <linux/pcs-lynx.h>
10 #define SGMII_CLOCK_PERIOD_NS 8 /* PCS is clocked at 125 MHz */
31 #define phylink_pcs_to_lynx(pl_pcs) container_of((pl_pcs), struct lynx_pcs, pcs)
33 static void lynx_pcs_get_state_usxgmii(struct mdio_device *pcs, in lynx_pcs_get_state_usxgmii() argument
36 struct mii_bus *bus = pcs->bus; in lynx_pcs_get_state_usxgmii()
37 int addr = pcs->addr; in lynx_pcs_get_state_usxgmii()
56 static void lynx_pcs_get_state_2500basex(struct mdio_device *pcs, in lynx_pcs_get_state_2500basex() argument
59 struct mii_bus *bus = pcs->bus; in lynx_pcs_get_state_2500basex()
60 int addr = pcs->addr; in lynx_pcs_get_state_2500basex()
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| D | Makefile | 2 # Makefile for Linux PCS drivers
4 obj-$(CONFIG_PCS_XPCS) += pcs-xpcs.o
5 obj-$(CONFIG_PCS_LYNX) += pcs-lynx.o
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| D | Kconfig | 3 # PCS Layer Configuration
6 menu "PCS device drivers"
18 This module provides helpers to phylink for managing the Lynx PCS
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| /Linux-v5.10/include/linux/ |
| D | phylink.h | 64 * @pcs_poll: MAC PCS cannot provide link change interrupt
148 * Read the current inband link state from the MAC PCS, reporting the
195 * where the PCS and MAC are not tightly integrated.)
201 * the results of in-band negotiation/status from the MAC PCS should be used
265 * complete any necessary steps after the MAC and PCS have been configured
310 * where these settings are not automatically conveyed from the PCS block,
331 * struct phylink_pcs - PHYLINK PCS instance
333 * @poll: poll the PCS for link changes
335 * This structure is designed to be embedded within the PCS private data,
336 * and will be passed between phylink and the PCS.
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| D | pcs-lynx.h | 3 * Lynx PCS helpers
13 struct phylink_pcs pcs; member
19 void lynx_pcs_destroy(struct lynx_pcs *pcs);
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| /Linux-v5.10/drivers/gpu/drm/amd/amdgpu/ |
| D | amdgpu_xgmi.c | 68 {"XGMI PCS DataLossErr",
70 {"XGMI PCS TrainingErr",
72 {"XGMI PCS CRCErr",
74 {"XGMI PCS BERExceededErr",
76 {"XGMI PCS TxMetaDataErr",
78 {"XGMI PCS ReplayBufParityErr",
80 {"XGMI PCS DataParityErr",
82 {"XGMI PCS ReplayFifoOverflowErr",
84 {"XGMI PCS ReplayFifoUnderflowErr",
86 {"XGMI PCS ElasticFifoOverflowErr",
[all …]
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| /Linux-v5.10/drivers/clocksource/ |
| D | timer-pistachio.c | 73 struct pistachio_clocksource *pcs = to_pistachio_clocksource(cs); in pistachio_clocksource_read_cycles() local
82 raw_spin_lock_irqsave(&pcs->lock, flags); in pistachio_clocksource_read_cycles()
83 overflw = gpt_readl(pcs->base, TIMER_CURRENT_OVERFLOW_VALUE, 0); in pistachio_clocksource_read_cycles()
84 counter = gpt_readl(pcs->base, TIMER_CURRENT_VALUE, 0); in pistachio_clocksource_read_cycles()
85 raw_spin_unlock_irqrestore(&pcs->lock, flags); in pistachio_clocksource_read_cycles()
98 struct pistachio_clocksource *pcs = to_pistachio_clocksource(cs); in pistachio_clksrc_set_mode() local
101 val = gpt_readl(pcs->base, TIMER_CFG, timeridx); in pistachio_clksrc_set_mode()
107 gpt_writel(pcs->base, val, TIMER_CFG, timeridx); in pistachio_clksrc_set_mode()
112 struct pistachio_clocksource *pcs = to_pistachio_clocksource(cs); in pistachio_clksrc_enable() local
116 gpt_writel(pcs->base, RELOAD_VALUE, TIMER_RELOAD_VALUE, timeridx); in pistachio_clksrc_enable()
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| /Linux-v5.10/drivers/net/ethernet/freescale/dpaa2/ |
| D | dpaa2-mac.c | 263 node = of_parse_phandle(dpmac_node, "pcs-handle", 0); in dpaa2_pcs_create()
266 netdev_warn(mac->net_dev, "pcs-handle node not found\n"); in dpaa2_pcs_create()
271 netdev_err(mac->net_dev, "pcs-handle node not available\n"); in dpaa2_pcs_create()
281 mac->pcs = lynx_pcs_create(mdiodev); in dpaa2_pcs_create()
282 if (!mac->pcs) { in dpaa2_pcs_create()
293 struct lynx_pcs *pcs = mac->pcs; in dpaa2_pcs_destroy() local
295 if (pcs) { in dpaa2_pcs_destroy()
296 struct device *dev = &pcs->mdio->dev; in dpaa2_pcs_destroy()
297 lynx_pcs_destroy(pcs); in dpaa2_pcs_destroy()
299 mac->pcs = NULL; in dpaa2_pcs_destroy()
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| D | dpaa2-mac.h | 10 #include <linux/pcs-lynx.h>
25 struct lynx_pcs *pcs; member
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| /Linux-v5.10/drivers/net/phy/ |
| D | phylink.c | 46 struct phylink_pcs *pcs; member
375 /* Check if MAC/PCS also supports Autoneg. */ in phylink_parse_mode()
431 pl->pcs_ops->pcs_an_restart(pl->pcs); in phylink_mac_pcs_an_restart()
457 err = pl->pcs_ops->pcs_config(pl->pcs, pl->cur_link_an_mode, in phylink_major_config()
482 * If we have a separate PCS, we only need to call its pcs_config() method,
506 /* Modern PCS-based method; update the advert at the PCS, and in phylink_change_inband_advert()
510 ret = pl->pcs_ops->pcs_config(pl->pcs, pl->cur_link_an_mode, in phylink_change_inband_advert()
537 pl->pcs_ops->pcs_get_state(pl->pcs, state); in phylink_mac_pcs_get_state()
610 pl->pcs_ops->pcs_link_up(pl->pcs, pl->cur_link_an_mode, in phylink_link_up()
709 * old mac_config() method to configure the MAC/PCS in phylink_resolve()
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| /Linux-v5.10/arch/mips/cavium-octeon/executive/ |
| D | cvmx-helper-sgmii.c | 65 * Write PCS*_LINK*_TIMER_COUNT_REG[COUNT] with the in __cvmx_helper_sgmii_hardware_init_one_time()
88 * 1000BASE-X mode, tx_Config_Reg<D15:D0> is PCS*_AN*_ADV_REG. in __cvmx_helper_sgmii_hardware_init_one_time()
90 * PCS*_SGM*_AN_ADV_REG. In SGMII MAC mode, in __cvmx_helper_sgmii_hardware_init_one_time()
142 * Take PCS through a reset sequence. in __cvmx_helper_sgmii_hardware_init_link()
143 * PCS*_MR*_CONTROL_REG[PWR_DN] should be cleared to zero. in __cvmx_helper_sgmii_hardware_init_link()
144 * Write PCS*_MR*_CONTROL_REG[RESET]=1 (while not changing the in __cvmx_helper_sgmii_hardware_init_link()
145 * value of the other PCS*_MR*_CONTROL_REG bits). Read in __cvmx_helper_sgmii_hardware_init_link()
146 * PCS*_MR*_CONTROL_REG[RESET] until it changes value to in __cvmx_helper_sgmii_hardware_init_link()
166 * Write PCS*_MR*_CONTROL_REG[RST_AN]=1 to ensure a fresh in __cvmx_helper_sgmii_hardware_init_link()
176 * Wait for PCS*_MR*_STATUS_REG[AN_CPT] to be set, indicating in __cvmx_helper_sgmii_hardware_init_link()
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| /Linux-v5.10/drivers/net/fddi/skfp/ |
| D | pcmplc.c | 1853 struct pcm_state *pcs ; in pcm_get_state() local
1860 for (i = 0, phy = smc->y, pcs = state->pcm_state ; i < NUMPHYS ; in pcm_get_state()
1861 i++ , phy++, pcs++ ) { in pcm_get_state()
1863 pcs->pcm_type = (u_char) mib->fddiPORTMy_Type ; in pcm_get_state()
1864 pcs->pcm_state = (u_char) mib->fddiPORTPCMState ; in pcm_get_state()
1865 pcs->pcm_mode = phy->pc_mode ; in pcm_get_state()
1866 pcs->pcm_neighbor = (u_char) mib->fddiPORTNeighborType ; in pcm_get_state()
1867 pcs->pcm_bsf = mib->fddiPORTBS_Flag ; in pcm_get_state()
1868 pcs->pcm_lsf = phy->ls_flag ; in pcm_get_state()
1869 pcs->pcm_lct_fail = (u_char) mib->fddiPORTLCTFail_Ct ; in pcm_get_state()
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| /Linux-v5.10/drivers/phy/qualcomm/ |
| D | phy-qcom-qmp.c | 122 /* PCS registers */
1834 /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
1888 /* true, if PCS block has no separate SW_RESET register */
1905 * @pcs: iomapped memory space for lane's pcs
1921 void __iomem *pcs; member
2689 qphy->pcs + QSERDES_V3_DP_PHY_PD_CTL); in qcom_qmp_phy_dp_aux_init()
2696 writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_V3_DP_PHY_PD_CTL); in qcom_qmp_phy_dp_aux_init()
2702 qphy->pcs + QSERDES_V3_DP_PHY_PD_CTL); in qcom_qmp_phy_dp_aux_init()
2710 writel(0x00, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG0); in qcom_qmp_phy_dp_aux_init()
2711 writel(0x13, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG1); in qcom_qmp_phy_dp_aux_init()
[all …]
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| /Linux-v5.10/drivers/net/ethernet/freescale/enetc/ |
| D | enetc_pf.c | 790 struct mdio_device *pcs; in enetc_imdio_create() local
814 pcs = mdio_device_create(bus, 0); in enetc_imdio_create()
815 if (IS_ERR(pcs)) { in enetc_imdio_create()
816 err = PTR_ERR(pcs); in enetc_imdio_create()
817 dev_err(dev, "cannot create pcs (%d)\n", err); in enetc_imdio_create()
821 pcs_lynx = lynx_pcs_create(pcs); in enetc_imdio_create()
823 mdio_device_free(pcs); in enetc_imdio_create()
825 dev_err(dev, "cannot create lynx pcs (%d)\n", err); in enetc_imdio_create()
830 pf->pcs = pcs_lynx; in enetc_imdio_create()
843 if (pf->pcs) { in enetc_imdio_remove()
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| /Linux-v5.10/Documentation/networking/device_drivers/ethernet/freescale/dpaa2/ |
| D | mac-phy-support.rst | 54 | MC firmware polling MAC PCS for link |
56 | | PCS | | PCS | | PCS | | PCS | |
65 the MC firmware by polling the MAC PCS. Without the need to register a
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| /Linux-v5.10/include/uapi/linux/ |
| D | mdio.h | 63 #define MDIO_PCS_10GBX_STAT1 24 /* 10GBASE-X PCS status 1 */
64 #define MDIO_PCS_10GBRT_STAT1 32 /* 10GBASE-R/-T PCS status 1 */
65 #define MDIO_PCS_10GBRT_STAT2 33 /* 10GBASE-R/-T PCS status 2 */
158 #define MDIO_PCS_CTRL2_TYPE 0x0003 /* PCS type selection */
240 /* PCS 10GBASE-R/-T status register 1. */
243 /* PCS 10GBASE-R/-T status register 2. */
296 #define MDIO_PMA_LASI_RX_PCSLFLT 0x0008 /* PCS RX local fault */
303 #define MDIO_PMA_LASI_TX_PCSLFLT 0x0008 /* PCS TX local fault */
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| /Linux-v5.10/drivers/net/ethernet/sun/ |
| D | sungem.h | 51 #define GREG_STAT_PCS 0x00002000 /* PCS signalled interrupt */
685 /* PCS/Serialink Registers */
686 #define PCS_MIICTRL 0x9000UL /* PCS MII Control Register */
687 #define PCS_MIISTAT 0x9004UL /* PCS MII Status Register */
688 #define PCS_MIIADV 0x9008UL /* PCS MII Advertisement Reg */
689 #define PCS_MIILP 0x900CUL /* PCS MII Link Partner Ability */
690 #define PCS_CFG 0x9010UL /* PCS Configuration Register */
691 #define PCS_SMACHINE 0x9014UL /* PCS State Machine Register */
692 #define PCS_ISTAT 0x9018UL /* PCS Interrupt Status Reg */
710 #define PCS_MIICTRL_RST 0x00008000 /* Resets PCS, self clearing */
[all …]
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| /Linux-v5.10/Documentation/devicetree/bindings/phy/ |
| D | ti-phy.txt | 13 set PCS delay value.
58 - syscon-pcs : phandle/offset pair. Phandle to the system control module and the
59 register offset to write the PCS delay value.
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| /Linux-v5.10/drivers/net/dsa/ocelot/ |
| D | seville_vsc9953.c | 10 #include <linux/pcs-lynx.h>
1075 felix->pcs = devm_kcalloc(dev, felix->info->num_ports, in vsc9953_mdio_bus_alloc()
1078 if (!felix->pcs) { in vsc9953_mdio_bus_alloc()
1079 dev_err(dev, "failed to allocate array for PCS PHYs\n"); in vsc9953_mdio_bus_alloc()
1106 struct mdio_device *pcs; in vsc9953_mdio_bus_alloc() local
1115 pcs = mdio_device_create(felix->imdio, addr); in vsc9953_mdio_bus_alloc()
1116 if (IS_ERR(pcs)) in vsc9953_mdio_bus_alloc()
1119 lynx = lynx_pcs_create(pcs); in vsc9953_mdio_bus_alloc()
1121 mdio_device_free(pcs); in vsc9953_mdio_bus_alloc()
1125 felix->pcs[port] = lynx; in vsc9953_mdio_bus_alloc()
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| /Linux-v5.10/drivers/net/ethernet/dlink/ |
| D | dl2k.h | 261 /* PCS register */
309 /* Physical Coding Sublayer Management (PCS) */
310 /* PCS control and status registers bitmap as the same as MII */
311 /* PCS Extended Status register bitmap as the same as MII */
312 /* PCS ANAR */
321 /* PCS ANLPAR */
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