Searched full:p5600 (Results 1 – 14 of 14) sorted by relevance
30 | +----+------|- MIPS P5600 cores48 to create a clock for the MIPS P5600 cores, the embedded DDR controller,78 clocks consumer (like P5600 cores or DDR controller) or passed over a CCU
33 | +----+------|- MIPS P5600 cores
54 #define MODULE_PROC_FAMILY "P5600 "
700 /* Config6 feature bits for proAptiv/P5600 */
15 tune the MIPS P5600 CM2 L2 cache performance up. In particular it's possible
15 high-speed peripheral IP-cores with RAM controller and with MIPS P5600
62 peripheral IP-cores with RAM controller and with MIPS P5600 cores on
74 Baikal-T1 CPU is based on the MIPS P5600 Warrior IP-core. The CPU
389 op_model_mipsxx_ops.cpu_type = "mips/P5600"; in mipsxx_init()
1612 bool "MIPS Warrior P5600"1624 Choose this option to build a kernel for MIPS Warrior P5600 CPU.1627 level features like up to six P5600 calculation cores, CM2 with L21847 Addressing (XPA) on your MIPS32 core (such as P5600 series). The
155 cflags-$(CONFIG_CPU_P5600) += -march=p5600 -Wa,--trap -modd-spreg
1722 /* P5600 */2016 mipspmu.name = "mips/P5600"; in init_hw_perf_events()
1466 __cpu_name[cpu] = "MIPS P5600"; in cpu_probe_mips()
998 * P5600 generates GPSI on guest MTC0 LLAddr. in kvm_vz_gpsi_cop0()
