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/Linux-v5.15/Documentation/devicetree/bindings/arm/tegra/
Dnvidia,tegra20-pmc.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra20-pmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jonathan Hunter <jonathanh@nvidia.com>
16 - nvidia,tegra20-pmc
17 - nvidia,tegra20-pmc
18 - nvidia,tegra30-pmc
19 - nvidia,tegra114-pmc
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/Linux-v5.15/kernel/time/
Dntp.c1 // SPDX-License-Identifier: GPL-2.0
5 * This code was mainly moved from kernel/timer.c and kernel/time.c
16 #include <linux/time.h>
49 * phase-lock loop variables
62 /* time adjustment (nsecs): */
65 /* pll time constant: */
77 /* time at last adjustment (secs): */
82 /* constant (boot-param configurable) NTP tick adjustment (upscaled) */
91 * The following variables are used when a pulse-per-second (PPS) signal
123 * Otherwise, reduce the offset by a fixed factor times the time constant.
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/Linux-v5.15/Documentation/networking/dsa/
Dsja1105.rst8 The NXP SJA1105 is a family of 10 SPI-managed automotive switches:
10 - SJA1105E: First generation, no TTEthernet
11 - SJA1105T: First generation, TTEthernet
12 - SJA1105P: Second generation, no TTEthernet, no SGMII
13 - SJA1105Q: Second generation, TTEthernet, no SGMII
14 - SJA1105R: Second generation, no TTEthernet, SGMII
15 - SJA1105S: Second generation, TTEthernet, SGMII
16 - SJA1110A: Third generation, TTEthernet, SGMII, integrated 100base-T1 and
17 100base-TX PHYs
18 - SJA1110B: Third generation, TTEthernet, SGMII, 100base-T1, 100base-TX
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/Linux-v5.15/Documentation/admin-guide/media/
Dbttv.rst1 .. SPDX-License-Identifier: GPL-2.0
8 ----------------------
12 ./scripts/config -e PCI
13 ./scripts/config -m I2C
14 ./scripts/config -m INPUT
15 ./scripts/config -m MEDIA_SUPPORT
16 ./scripts/config -e MEDIA_PCI_SUPPORT
17 ./scripts/config -e MEDIA_ANALOG_TV_SUPPORT
18 ./scripts/config -e MEDIA_DIGITAL_TV_SUPPORT
19 ./scripts/config -e MEDIA_RADIO_SUPPORT
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/Linux-v5.15/drivers/net/ethernet/dec/tulip/
Dde4x5.h16 #define DE4X5_BMR iobase+(0x000 << lp->bus) /* Bus Mode Register */
17 #define DE4X5_TPD iobase+(0x008 << lp->bus) /* Transmit Poll Demand Reg */
18 #define DE4X5_RPD iobase+(0x010 << lp->bus) /* Receive Poll Demand Reg */
19 #define DE4X5_RRBA iobase+(0x018 << lp->bus) /* RX Ring Base Address Reg */
20 #define DE4X5_TRBA iobase+(0x020 << lp->bus) /* TX Ring Base Address Reg */
21 #define DE4X5_STS iobase+(0x028 << lp->bus) /* Status Register */
22 #define DE4X5_OMR iobase+(0x030 << lp->bus) /* Operation Mode Register */
23 #define DE4X5_IMR iobase+(0x038 << lp->bus) /* Interrupt Mask Register */
24 #define DE4X5_MFC iobase+(0x040 << lp->bus) /* Missed Frame Counter */
25 #define DE4X5_APROM iobase+(0x048 << lp->bus) /* Ethernet Address PROM */
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/Linux-v5.15/drivers/misc/cardreader/
Drtsx_pcr.c1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* Driver for Realtek PCI-Express card reader
4 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
13 #include <linux/dma-mapping.h>
85 if (pcr->aspm_enabled == enable) in rtsx_comm_set_aspm()
88 if (pcr->aspm_mode == ASPM_MODE_CFG) { in rtsx_comm_set_aspm()
89 pcie_capability_clear_and_set_word(pcr->pci, PCI_EXP_LNKCTL, in rtsx_comm_set_aspm()
91 enable ? pcr->aspm_en : 0); in rtsx_comm_set_aspm()
92 } else if (pcr->aspm_mode == ASPM_MODE_REG) { in rtsx_comm_set_aspm()
93 if (pcr->aspm_en & 0x02) in rtsx_comm_set_aspm()
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/Linux-v5.15/drivers/clk/tegra/
Dclk-pll.c1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <linux/clk-provider.h>
31 #define PLL_MISC_CPCON_MASK ((1 << PLL_MISC_CPCON_WIDTH) - 1)
34 #define PLL_MISC_LFCON_MASK ((1 << PLL_MISC_LFCON_WIDTH) - 1)
37 #define PLL_MISC_VCOCON_MASK ((1 << PLL_MISC_VCOCON_WIDTH) - 1)
230 #define pll_readl(offset, p) readl_relaxed(p->clk_base + offset)
231 #define pll_readl_base(p) pll_readl(p->params->base_reg, p)
232 #define pll_readl_misc(p) pll_readl(p->params->misc_reg, p)
233 #define pll_override_readl(offset, p) readl_relaxed(p->pmc + offset)
234 #define pll_readl_sdm_din(p) pll_readl(p->params->sdm_din_reg, p)
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Dclk-dfll.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * clk-dfll.c - Tegra DFLL clock source common code
5 * Copyright (C) 2012-2019 NVIDIA Corporation. All rights reserved.
12 * "CL-DVFS". To try to avoid confusion, this code refers to them
18 * DFLL can be operated in either open-loop mode or closed-loop mode.
19 * In open-loop mode, the DFLL generates an output clock appropriate
20 * to the supply voltage. In closed-loop mode, when configured with a
26 * CPU cycle time will vary. This has implications for
27 * performance-measurement code and any code that relies on the CPU
28 * cycle time to delay for a certain length of time.
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Dclk-tegra210.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2012-2020 NVIDIA CORPORATION. All rights reserved.
8 #include <linux/clk-provider.h>
17 #include <dt-bindings/clock/tegra210-car.h>
18 #include <dt-bindings/reset/tegra210-car.h>
23 #include "clk-id.h"
264 * SDM fractional divisor is 16-bit 2's complement signed number within
265 * (-2^12 ... 2^12-1) range. Represented in PLL data structure as unsigned
266 * 16-bit value, with "0" divisor mapped to 0xFFFF. Data "0" is used to
275 #define sdin_get_n_eff(cfg) ((cfg)->n * PLL_SDM_COEFF + ((cfg)->sdm_data ? \
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/Linux-v5.15/drivers/net/wireless/ralink/rt2x00/
Drt2800.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 Copyright (C) 2004 - 2010 Ivo van Doorn <IvDoorn@gmail.com>
196 * Ring oscillator configuration
283 * AUX_CTRL: Aux/PCI-E related configuration
573 * HOST-MCU shared memory
773 * 0: 1-BSSID mode (BSS index = 0)
774 * 1: 2-BSSID mode (BSS index: Byte5, bit 0)
775 * 2: 4-BSSID mode (BSS index: byte5, bit 0 - 1)
776 * 3: 8-BSSID mode (BSS index: byte5, bit 0 - 2)
852 * ON_PERIOD: LED active time (ms) during TX (only used for LED mode 1)
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Drt2800lib.c1 // SPDX-License-Identifier: GPL-2.0-or-later
24 #include <linux/crc-ccitt.h>
46 * between each attampt. When the busy bit is still set at that time,
86 mutex_lock(&rt2x00dev->csr_mutex); in rt2800_bbp_write()
103 mutex_unlock(&rt2x00dev->csr_mutex); in rt2800_bbp_write()
111 mutex_lock(&rt2x00dev->csr_mutex); in rt2800_bbp_read()
117 * returns the correct value, if at any time the register in rt2800_bbp_read()
118 * doesn't become available in time, reg will be 0xffffffff in rt2800_bbp_read()
135 mutex_unlock(&rt2x00dev->csr_mutex); in rt2800_bbp_read()
145 mutex_lock(&rt2x00dev->csr_mutex); in rt2800_rfcsr_write()
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/Linux-v5.15/drivers/media/dvb-frontends/drx39xyj/
Ddrx_driver.h2 Copyright (c), 2004-2005,2007-2010 Trident Microsystems, Inc.
60 /*------------------------------------------------------------------------------
62 ------------------------------------------------------------------------------*/
69 * \retval -EIO Initialization failed.
78 * \retval -EIO Termination failed.
98 * \retval -EIO Failure.
99 * \retval -EINVAL Parameter 'wcount' is not zero but parameter
133 #define TUNER_MODE_SUB0 0x0001 /* for sub-mode (e.g. RF-AGC setting) */
134 #define TUNER_MODE_SUB1 0x0002 /* for sub-mode (e.g. RF-AGC setting) */
135 #define TUNER_MODE_SUB2 0x0004 /* for sub-mode (e.g. RF-AGC setting) */
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