| /Linux-v6.1/drivers/clk/ |
| D | clk-multiplier.c | 15 static inline u32 clk_mult_readl(struct clk_multiplier *mult) in clk_mult_readl() argument
17 if (mult->flags & CLK_MULTIPLIER_BIG_ENDIAN) in clk_mult_readl()
18 return ioread32be(mult->reg); in clk_mult_readl()
20 return readl(mult->reg); in clk_mult_readl()
23 static inline void clk_mult_writel(struct clk_multiplier *mult, u32 val) in clk_mult_writel() argument
25 if (mult->flags & CLK_MULTIPLIER_BIG_ENDIAN) in clk_mult_writel()
26 iowrite32be(val, mult->reg); in clk_mult_writel()
28 writel(val, mult->reg); in clk_mult_writel()
31 static unsigned long __get_mult(struct clk_multiplier *mult, in __get_mult() argument
35 if (mult->flags & CLK_MULTIPLIER_ROUND_CLOSEST) in __get_mult()
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| D | clk-fixed-factor.c | 18 * rate - rate is fixed. clk->rate = parent->rate / div * mult
28 rate = (unsigned long long int)parent_rate * fix->mult; in clk_factor_recalc_rate()
41 best_parent = (rate / fix->mult) * fix->div; in clk_factor_round_rate()
45 return (*prate / fix->div) * fix->mult; in clk_factor_round_rate()
83 unsigned long flags, unsigned int mult, unsigned int div, in __clk_hw_register_fixed_factor() argument
105 fix->mult = mult; in __clk_hw_register_fixed_factor()
144 * @mult: multiplier
152 unsigned int mult, unsigned int div) in devm_clk_hw_register_fixed_factor_index() argument
155 flags, mult, div, true); in devm_clk_hw_register_fixed_factor_index()
166 * @mult: multiplier
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| /Linux-v6.1/drivers/clk/sunxi-ng/ |
| D | ccu_mult.c | 14 unsigned long mult, min, max; member
18 struct _ccu_mult *mult) in ccu_mult_find_best() argument
23 if (_mult < mult->min) in ccu_mult_find_best()
24 _mult = mult->min; in ccu_mult_find_best()
26 if (_mult > mult->max) in ccu_mult_find_best()
27 _mult = mult->max; in ccu_mult_find_best()
29 mult->mult = _mult; in ccu_mult_find_best()
41 _cm.min = cm->mult.min; in ccu_mult_round_rate()
43 if (cm->mult.max) in ccu_mult_round_rate()
44 _cm.max = cm->mult.max; in ccu_mult_round_rate()
[all …]
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| /Linux-v6.1/drivers/clk/renesas/ |
| D | rcar-gen3-cpg.c | 37 #define CPG_PLLnCR_STC_MASK GENMASK(30, 24) /* PLL Circuit Mult. Ratio */
56 unsigned int mult; in cpg_pll_clk_recalc_rate() local
60 mult = (val >> __ffs(CPG_PLLnCR_STC_MASK)) + 1; in cpg_pll_clk_recalc_rate()
62 return parent_rate * mult * pll_clk->fixed_mult; in cpg_pll_clk_recalc_rate()
69 unsigned int min_mult, max_mult, mult; in cpg_pll_clk_determine_rate() local
78 mult = DIV_ROUND_CLOSEST_ULL(req->rate, prate); in cpg_pll_clk_determine_rate()
79 mult = clamp(mult, min_mult, max_mult); in cpg_pll_clk_determine_rate()
81 req->rate = prate * mult; in cpg_pll_clk_determine_rate()
89 unsigned int mult, i; in cpg_pll_clk_set_rate() local
92 mult = DIV_ROUND_CLOSEST_ULL(rate, parent_rate * pll_clk->fixed_mult); in cpg_pll_clk_set_rate()
[all …]
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| D | rcar-gen4-cpg.c | 52 unsigned int mult; in cpg_z_clk_recalc_rate() local
56 mult = 32 - (val >> __ffs(zclk->mask)); in cpg_z_clk_recalc_rate()
58 return DIV_ROUND_CLOSEST_ULL((u64)parent_rate * mult, in cpg_z_clk_recalc_rate()
66 unsigned int min_mult, max_mult, mult; in cpg_z_clk_determine_rate() local
86 mult = DIV_ROUND_CLOSEST_ULL(rate * 32ULL, prate); in cpg_z_clk_determine_rate()
87 mult = clamp(mult, min_mult, max_mult); in cpg_z_clk_determine_rate()
89 req->rate = DIV_ROUND_CLOSEST_ULL((u64)prate * mult, 32); in cpg_z_clk_determine_rate()
97 unsigned int mult; in cpg_z_clk_set_rate() local
100 mult = DIV64_U64_ROUND_CLOSEST(rate * 32ULL * zclk->fixed_div, in cpg_z_clk_set_rate()
102 mult = clamp(mult, 1U, 32U); in cpg_z_clk_set_rate()
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| D | rcar-gen2-cpg.c | 41 * rate - rate is adjustable. clk->rate = parent->rate * mult / 32
57 unsigned int mult; in cpg_z_clk_recalc_rate() local
61 mult = 32 - val; in cpg_z_clk_recalc_rate()
63 return div_u64((u64)parent_rate * mult, 32); in cpg_z_clk_recalc_rate()
70 unsigned int min_mult, max_mult, mult; in cpg_z_clk_determine_rate() local
77 mult = div64_ul(req->rate * 32ULL, prate); in cpg_z_clk_determine_rate()
78 mult = clamp(mult, min_mult, max_mult); in cpg_z_clk_determine_rate()
80 req->rate = div_u64((u64)prate * mult, 32); in cpg_z_clk_determine_rate()
88 unsigned int mult; in cpg_z_clk_set_rate() local
92 mult = div64_ul(rate * 32ULL, parent_rate); in cpg_z_clk_set_rate()
[all …]
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| D | clk-sh73a0.c | 80 unsigned int mult = 1; in sh73a0_cpg_register_clock() local
111 mult = ((readl(enable_reg) >> 24) & 0x3f) + 1; in sh73a0_cpg_register_clock()
115 mult *= 2; in sh73a0_cpg_register_clock()
123 mult = readl(dsi_reg); in sh73a0_cpg_register_clock()
124 if (!(mult & 0x8000)) in sh73a0_cpg_register_clock()
125 mult = 1; in sh73a0_cpg_register_clock()
127 mult = (mult & 0x3f) + 1; in sh73a0_cpg_register_clock()
153 mult, div); in sh73a0_cpg_register_clock()
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| /Linux-v6.1/drivers/clk/sunxi/ |
| D | clk-sun4i-pll3.c | 24 struct clk_multiplier *mult; in sun4i_a10_pll3_setup() local
48 mult = kzalloc(sizeof(*mult), GFP_KERNEL); in sun4i_a10_pll3_setup()
49 if (!mult) in sun4i_a10_pll3_setup()
52 mult->reg = reg; in sun4i_a10_pll3_setup()
53 mult->shift = SUN4I_A10_PLL3_DIV_SHIFT; in sun4i_a10_pll3_setup()
54 mult->width = SUN4I_A10_PLL3_DIV_WIDTH; in sun4i_a10_pll3_setup()
55 mult->lock = &sun4i_a10_pll3_lock; in sun4i_a10_pll3_setup()
60 &mult->hw, &clk_multiplier_ops, in sun4i_a10_pll3_setup()
80 kfree(mult); in sun4i_a10_pll3_setup()
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| D | clk-a10-pll2.c | 44 struct clk_multiplier *mult; in sun4i_pll2_setup() local
83 mult = kzalloc(sizeof(struct clk_multiplier), GFP_KERNEL); in sun4i_pll2_setup()
84 if (!mult) in sun4i_pll2_setup()
87 mult->reg = reg; in sun4i_pll2_setup()
88 mult->shift = SUN4I_PLL2_N_SHIFT; in sun4i_pll2_setup()
89 mult->width = 7; in sun4i_pll2_setup()
90 mult->flags = CLK_MULTIPLIER_ZERO_BYPASS | in sun4i_pll2_setup()
92 mult->lock = &sun4i_a10_pll2_lock; in sun4i_pll2_setup()
98 &mult->hw, &clk_multiplier_ops, in sun4i_pll2_setup()
168 kfree(mult); in sun4i_pll2_setup()
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| /Linux-v6.1/drivers/clk/imx/ |
| D | clk-pllv4.c | 49 /* Valid PLL MULT Table */
78 u32 mult, mfn, mfd; in clk_pllv4_recalc_rate() local
81 mult = readl_relaxed(pll->base + pll->cfg_offset); in clk_pllv4_recalc_rate()
82 mult &= BM_PLL_MULT; in clk_pllv4_recalc_rate()
83 mult >>= BP_PLL_MULT; in clk_pllv4_recalc_rate()
91 return (parent_rate * mult) + (u32)temp64; in clk_pllv4_recalc_rate()
141 static bool clk_pllv4_is_valid_mult(unsigned int mult) in clk_pllv4_is_valid_mult() argument
145 /* check if mult is in valid MULT table */ in clk_pllv4_is_valid_mult()
147 if (pllv4_mult_table[i] == mult) in clk_pllv4_is_valid_mult()
158 u32 val, mult, mfn, mfd = DEFAULT_MFD; in clk_pllv4_set_rate() local
[all …]
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| /Linux-v6.1/drivers/clk/mvebu/ |
| D | orion.c | 60 int *mult, int *div) in mv88f5181_get_clk_ratio() argument
65 *mult = 1; in mv88f5181_get_clk_ratio()
68 *mult = 1; in mv88f5181_get_clk_ratio()
71 *mult = 0; in mv88f5181_get_clk_ratio()
128 int *mult, int *div) in mv88f5182_get_clk_ratio() argument
133 *mult = 1; in mv88f5182_get_clk_ratio()
136 *mult = 1; in mv88f5182_get_clk_ratio()
139 *mult = 0; in mv88f5182_get_clk_ratio()
185 int *mult, int *div) in mv88f5281_get_clk_ratio() argument
190 *mult = 1; in mv88f5281_get_clk_ratio()
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| /Linux-v6.1/include/linux/ |
| D | clocksource.h | 42 * @mult: Cycle to nanosecond multiplier
45 * @maxadj: Maximum adjustment value to mult (~11%)
99 u32 mult; member
150 * mult/2^shift = ns/cyc in clocksource_freq2mult()
151 * mult = ns/cyc * 2^shift in clocksource_freq2mult()
152 * mult = from/freq * 2^shift in clocksource_freq2mult()
153 * mult = from * 2^shift / freq in clocksource_freq2mult()
154 * mult = (from<<shift) / freq in clocksource_freq2mult()
165 * clocksource_khz2mult - calculates mult from khz and shift
178 * clocksource_hz2mult - calculates mult from hz and shift
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| /Linux-v6.1/sound/core/ |
| D | pcm_timer.c | 21 unsigned long rate, mult, fsize, l, post; in snd_pcm_timer_resolution_change() local
24 mult = 1000000000; in snd_pcm_timer_resolution_change()
28 l = gcd(mult, rate); in snd_pcm_timer_resolution_change()
29 mult /= l; in snd_pcm_timer_resolution_change()
38 while ((mult * fsize) / fsize != mult) { in snd_pcm_timer_resolution_change()
39 mult /= 2; in snd_pcm_timer_resolution_change()
49 runtime->timer_resolution = (mult * fsize / rate) * post; in snd_pcm_timer_resolution_change()
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| /Linux-v6.1/drivers/iio/imu/inv_icm42600/ |
| D | inv_icm42600_timestamp.c | 50 ts->mult = default_period / INV_ICM42600_TIMESTAMP_PERIOD; in inv_icm42600_timestamp_init()
82 static bool inv_validate_period(uint32_t period, uint32_t mult) in inv_validate_period() argument
88 period_min = INV_ICM42600_TIMESTAMP_MIN_PERIOD(chip_period) * mult; in inv_validate_period()
89 period_max = INV_ICM42600_TIMESTAMP_MAX_PERIOD(chip_period) * mult; in inv_validate_period()
97 uint32_t mult, uint32_t period) in inv_compute_chip_period() argument
101 if (!inv_validate_period(period, mult)) in inv_compute_chip_period()
105 new_chip_period = period / mult; in inv_compute_chip_period()
136 ts->period = ts->mult * ts->chip_period.val; in inv_icm42600_timestamp_interrupt()
177 ts->mult = ts->new_mult; in inv_icm42600_timestamp_apply_odr()
179 ts->period = ts->mult * ts->chip_period.val; in inv_icm42600_timestamp_apply_odr()
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| /Linux-v6.1/arch/arm/boot/dts/ |
| D | omap36xx-omap3430es2plus-clocks.dtsi | 49 clock-mult = <1>;
80 clock-mult = <1>;
103 clock-mult = <1>;
111 clock-mult = <1>;
119 clock-mult = <1>;
127 clock-mult = <1>;
135 clock-mult = <1>;
143 clock-mult = <1>;
151 clock-mult = <1>;
159 clock-mult = <1>;
[all …]
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| D | am33xx-clocks.dtsi | 22 clock-mult = <1>;
31 clock-mult = <1>;
40 clock-mult = <1>;
49 clock-mult = <1>;
58 clock-mult = <1>;
67 clock-mult = <1>;
76 clock-mult = <1>;
85 clock-mult = <1>;
94 clock-mult = <1>;
103 clock-mult = <1>;
[all …]
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| D | am43xx-clocks.dtsi | 40 clock-mult = <1>;
49 clock-mult = <1>;
58 clock-mult = <1>;
67 clock-mult = <1>;
76 clock-mult = <1>;
85 clock-mult = <1>;
94 clock-mult = <1>;
103 clock-mult = <1>;
112 clock-mult = <1>;
121 clock-mult = <1>;
[all …]
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| D | keystone-clocks.dtsi | 28 clock-mult = <1>;
37 clock-mult = <1>;
66 clock-mult = <1>;
75 clock-mult = <1>;
84 clock-mult = <1>;
93 clock-mult = <1>;
102 clock-mult = <1>;
111 clock-mult = <1>;
120 clock-mult = <1>;
129 clock-mult = <1>;
[all …]
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| /Linux-v6.1/arch/arm/mach-omap2/ |
| D | clkt2xxx_dpllcore.c | 112 u32 cur_rate, low, mult, div, valid_rate, done_rate; in omap2_reprogram_dpllcore() local
118 mult = omap2xxx_cm_get_core_clk_src(); in omap2_reprogram_dpllcore()
120 if ((rate == (cur_rate / 2)) && (mult == 2)) { in omap2_reprogram_dpllcore()
122 } else if ((rate == (cur_rate * 2)) && (mult == 1)) { in omap2_reprogram_dpllcore()
129 if (mult == 1) in omap2_reprogram_dpllcore()
147 mult = ((rate / 2) / 1000000); in omap2_reprogram_dpllcore()
151 mult = (rate / 1000000); in omap2_reprogram_dpllcore()
155 tmpset.cm_clksel1_pll |= (mult << __ffs(dd->div1_mask)); in omap2_reprogram_dpllcore()
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| /Linux-v6.1/arch/arm64/boot/dts/broadcom/stingray/ |
| D | stingray-clock.dtsi | 46 clock-mult = <1>;
132 clock-mult = <1>;
140 clock-mult = <1>;
149 clock-mult = <1>;
157 clock-mult = <1>;
165 clock-mult = <1>;
173 clock-mult = <1>;
181 clock-mult = <1>;
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| /Linux-v6.1/drivers/net/ethernet/pensando/ionic/ |
| D | ionic_phc.c | 311 ctx->cmd.lif_setphc.mult = cpu_to_le32(phc->cc.mult); in ionic_setphc_cmd()
342 phc->cc.mult = adj; in ionic_phc_adjfine()
524 u64 delay, diff, mult; in ionic_lif_alloc_phc() local
544 phc->cc.mult = le32_to_cpu(ionic->ident.dev.hwstamp_mult); in ionic_lif_alloc_phc()
547 if (!phc->cc.mult) { in ionic_lif_alloc_phc()
550 phc->cc.mult); in ionic_lif_alloc_phc()
556 dev_dbg(lif->ionic->dev, "Device PHC mask %#llx mult %u shift %u\n", in ionic_lif_alloc_phc()
557 phc->cc.mask, phc->cc.mult, phc->cc.shift); in ionic_lif_alloc_phc()
567 diff = U64_MAX / phc->cc.mult / 2; in ionic_lif_alloc_phc()
571 diff = DIV_ROUND_UP(diff, phc->cc.mult); in ionic_lif_alloc_phc()
[all …]
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| /Linux-v6.1/drivers/clk/ti/ |
| D | fixed-factor.c | 33 u32 div, mult; in of_ti_fixed_factor_clk_setup() local
41 if (of_property_read_u32(node, "ti,clock-mult", &mult)) { in of_ti_fixed_factor_clk_setup()
42 pr_err("%pOFn must have a clock-mult property\n", node); in of_ti_fixed_factor_clk_setup()
52 mult, div); in of_ti_fixed_factor_clk_setup()
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| /Linux-v6.1/kernel/time/ |
| D | clocksource.c | 24 * clocks_calc_mult_shift - calculate mult/shift factors for scaled math of clocks
25 * @mult: pointer to mult variable
31 * The function evaluates the shift/mult pair for the scaled math
40 * calculated mult and shift factors. This guarantees that no 64bit
42 * multiplied with the calculated mult factor. Larger ranges may
43 * reduce the conversion accuracy by choosing smaller mult and shift
47 clocks_calc_mult_shift(u32 *mult, u32 *shift, u32 from, u32 to, u32 maxsec) in clocks_calc_mult_shift() argument
63 * Find the conversion shift/mult pair which has the best in clocks_calc_mult_shift()
73 *mult = tmp; in clocks_calc_mult_shift()
235 wd_delay = clocksource_cyc2ns(wd_delta, watchdog->mult, in cs_watchdog_read()
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| /Linux-v6.1/drivers/thermal/broadcom/ |
| D | brcmstb_thermal.c | 107 unsigned int mult; member
124 int mult = priv->temp_params->mult; in avs_tmon_code_to_temp() local
126 return (offset - (int)((code & AVS_TMON_TEMP_MASK) * mult)); in avs_tmon_code_to_temp()
139 int mult = priv->temp_params->mult; in avs_tmon_temp_to_code() local
148 return (u32)(DIV_ROUND_UP(offset - temp, mult)); in avs_tmon_temp_to_code()
150 return (u32)((offset - temp) / mult); in avs_tmon_temp_to_code()
297 .mult = 557,
308 .mult = 487,
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| /Linux-v6.1/drivers/clk/x86/ |
| D | clk-cgu-pll.c | 21 * rate = (prate * mult + (prate * frac) / frac_div) / div
24 lgm_pll_calc_rate(unsigned long prate, unsigned int mult, in lgm_pll_calc_rate() argument
30 crate = rate64 * mult; in lgm_pll_calc_rate()
42 unsigned int div, mult, frac; in lgm_pll_recalc_rate() local
46 mult = lgm_get_clk_val(pll->membase, PLL_REF_DIV(pll->reg), 0, 12); in lgm_pll_recalc_rate()
54 return lgm_pll_calc_rate(prate, mult, div, frac, BIT(24)); in lgm_pll_recalc_rate()
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