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/Linux-v6.6/drivers/gpu/drm/bridge/imx/
DKconfig17 tristate "Freescale i.MX8QXP LVDS display bridge"
24 Freescale i.MX8qxp processor. Official name of LDB is pixel mapper.
45 tristate "Freescale i.MX8QXP pixel link to display pixel interface"
50 found in Freescale i.MX8qxp processor.
Dimx8qxp-pixel-link.c425 MODULE_DESCRIPTION("i.MX8QXP/QM display pixel link bridge driver");
Dimx8qxp-pxl2dpi.c483 MODULE_DESCRIPTION("i.MX8QXP pixel link to DPI bridge driver");
/Linux-v6.6/Documentation/devicetree/bindings/display/bridge/
Dfsl,imx8qxp-pxl2dpi.yaml7 title: Freescale i.MX8qxp Pixel Link to Display Pixel Interface
13 The Freescale i.MX8qxp Pixel Link to Display Pixel Interface(PXL2DPI)
19 The i.MX8qxp PXL2DPI is controlled by Control and Status Registers(CSR) module.
Dfsl,imx8qxp-ldb.yaml19 For i.MX8qxp LDB, each channel supports up to 24bpp parallel input color
/Linux-v6.6/Documentation/devicetree/bindings/bus/
Dfsl,imx8qxp-pixel-link-msi-bus.yaml7 title: Freescale i.MX8qxp Pixel Link Medium Speed Interconnect (MSI) Bus
13 i.MX8qxp pixel link MSI bus is used to control settings of PHYs, I/Os
18 i.MX8qxp pixel link MSI bus is a simple memory-mapped bus. Two input clocks,
/Linux-v6.6/drivers/firmware/imx/
DKconfig8 DSP exists on some i.MX8 processors (e.g i.MX8QM, i.MX8QXP).
Dimx-scu-soc.c87 return "i.MX8QXP"; in imx_scu_soc_name()
/Linux-v6.6/drivers/media/platform/nxp/imx8-isi/
Dimx8-isi-core.h3 * V4L2 Capture ISI subdev for i.MX8QXP/QM platform
5 * ISI is a Image Sensor Interface of i.MX8QXP/QM platform, which
Dimx8-isi-m2m.c3 * ISI V4L2 memory to memory driver for i.MX8QXP/QM platform
5 * ISI is a Image Sensor Interface of i.MX8QXP/QM platform, which
Dimx8-isi-pipe.c3 * V4L2 Capture ISI subdev driver for i.MX8QXP/QM platform
5 * ISI is a Image Sensor Interface of i.MX8QXP/QM platform, which
/Linux-v6.6/Documentation/devicetree/bindings/phy/
Dmixel,mipi-dsi-phy.yaml17 The Mixel PHY IP block found on i.MX8qxp is a combo PHY that can work
/Linux-v6.6/Documentation/devicetree/bindings/media/
Dnxp,imx8-jpeg.yaml7 title: i.MX8QXP/QM JPEG decoder/encoder
Damphion,vpu.yaml53 separately. NXP i.MX8QM SoC has one decoder and two encoder, i.MX8QXP SoC
/Linux-v6.6/Documentation/devicetree/bindings/clock/
Dimx8qxp-lpcg.yaml7 title: NXP i.MX8QXP LPCG (Low-Power Clock Gating) Clock
/Linux-v6.6/drivers/media/platform/nxp/imx-jpeg/
Dmxc-jpeg.h3 * i.MX8QXP/i.MX8QM JPEG encoder/decoder v4l2 driver
Dmxc-jpeg-hw.h3 * i.MX8QXP/i.MX8QM JPEG encoder/decoder v4l2 driver
Dmxc-jpeg-hw.c3 * i.MX8QXP/i.MX8QM JPEG encoder/decoder v4l2 driver
/Linux-v6.6/arch/arm64/boot/dts/freescale/
Dimx8qxp-ai_ml.dts12 model = "Einfochips i.MX8QXP AI_ML";
Dimx8qxp-mek.dts12 model = "Freescale i.MX8QXP MEK";
/Linux-v6.6/drivers/pinctrl/freescale/
Dpinctrl-imx8qxp.c240 MODULE_DESCRIPTION("NXP i.MX8QXP pinctrl driver");
/Linux-v6.6/drivers/remoteproc/
Dimx_dsp_rproc.c268 /* Specific configuration for i.MX8QXP */
951 * On i.MX8QM and i.MX8QXP there is multiple power domains
1034 * For i.MX8QXP and i.MX8QM, DSP should be started and stopped by System
/Linux-v6.6/drivers/clk/imx/
Dclk-imx8qxp.c314 MODULE_DESCRIPTION("NXP i.MX8QXP clock driver");
/Linux-v6.6/sound/soc/fsl/
Dfsl_mqs.c200 * But in i.MX8QM/i.MX8QXP the control register is moved in fsl_mqs_probe()
/Linux-v6.6/Documentation/devicetree/bindings/arm/
Dfsl.yaml1190 - description: i.MX8QXP based Boards
1193 - einfochips,imx8qxp-ai_ml # i.MX8QXP AI_ML Board
1194 - fsl,imx8qxp-mek # i.MX8QXP MEK Board
1204 - description: i.MX8QXP Boards with Toradex Colibri iMX8X Modules

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