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/Linux-v6.1/drivers/gpu/drm/bridge/imx/
DKconfig4 tristate "Freescale i.MX8QM LVDS display bridge"
10 Freescale i.MX8qm processor. Official name of LDB is pixel mapper.
22 tristate "Freescale i.MX8QM/QXP pixel combiner"
28 Freescale i.MX8qm/qxp processors.
31 tristate "Freescale i.MX8QM/QXP display pixel link"
37 Freescale i.MX8qm/qxp processors.
Dimx8qxp-pixel-combiner.c447 MODULE_DESCRIPTION("i.MX8QM/QXP pixel combiner bridge driver");
Dimx8qm-ldb-drv.c585 MODULE_DESCRIPTION("i.MX8QM LVDS Display Bridge(LDB)/Pixel Mapper bridge driver");
/Linux-v6.1/Documentation/devicetree/bindings/display/bridge/
Dfsl,imx8qxp-ldb.yaml7 title: Freescale i.MX8qm/qxp LVDS Display Bridge
13 The Freescale i.MX8qm/qxp LVDS Display Bridge(LDB) has two channels.
15 The i.MX8qm/qxp LDB is controlled by Control and Status Registers(CSR) module.
27 For i.MX8qm LDB, each channel additionally supports up to 30bpp parallel
33 A side note is that i.MX8qm/qxp LDB is officially called pixel mapper in
Dfsl,imx8qxp-pixel-link.yaml7 title: Freescale i.MX8qm/qxp Display Pixel Link
13 The Freescale i.MX8qm/qxp Display Pixel Link(DPL) forms a standard
21 The i.MX8qm/qxp Display Pixel Link is accessed via System Controller Unit(SCU)
Dfsl,imx8qxp-pixel-combiner.yaml7 title: Freescale i.MX8qm/qxp Pixel Combiner
13 The Freescale i.MX8qm/qxp Pixel Combiner takes two output streams from a
/Linux-v6.1/Documentation/devicetree/bindings/phy/
Dfsl,imx8qm-lvds-phy.yaml7 title: Mixel LVDS PHY for Freescale i.MX8qm SoC
13 The Mixel LVDS PHY IP block is found on Freescale i.MX8qm SoC.
23 The Mixel LVDS PHY found on Freescale i.MX8qm SoC is controlled
/Linux-v6.1/drivers/firmware/imx/
DKconfig8 DSP exists on some i.MX8 processors (e.g i.MX8QM, i.MX8QXP).
20 resource management. It exists on some i.MX8 processors. e.g. i.MX8QM
/Linux-v6.1/Documentation/devicetree/bindings/mfd/
Dfsl,imx8qxp-csr.yaml7 title: Freescale i.MX8qm/qxp Control and Status Registers Module Bindings
13 As a system controller, the Freescale i.MX8qm/qxp Control and Status
/Linux-v6.1/Documentation/devicetree/bindings/media/
Damphion,vpu.yaml53 separately. NXP i.MX8QM SoC has one decoder and two encoder, i.MX8QXP SoC
110 # Device node example for i.MX8QM platform:
/Linux-v6.1/drivers/phy/freescale/
DKconfig18 on NXP's i.MX8qm SoC.
/Linux-v6.1/Documentation/devicetree/bindings/pwm/
Dpwm-fsl-ftm.txt22 - "fsl,imx8qm-ftm-pwm" for PWM compatible with the one integrated on i.MX8QM
/Linux-v6.1/arch/arm64/boot/dts/freescale/
Dimx8qm-mek.dts12 model = "Freescale i.MX8QM MEK";
/Linux-v6.1/drivers/media/platform/nxp/imx-jpeg/
Dmxc-jpeg.h3 * i.MX8QXP/i.MX8QM JPEG encoder/decoder v4l2 driver
Dmxc-jpeg-hw.h3 * i.MX8QXP/i.MX8QM JPEG encoder/decoder v4l2 driver
Dmxc-jpeg-hw.c3 * i.MX8QXP/i.MX8QM JPEG encoder/decoder v4l2 driver
Dmxc-jpeg.c3 * V4L2 driver for the JPEG encoder/decoder from i.MX8QXP/i.MX8QM application
/Linux-v6.1/drivers/net/can/flexcan/
Dflexcan.h30 * MX8QM FlexCAN3 03.00.23.00 yes yes no no yes yes 64
/Linux-v6.1/Documentation/devicetree/bindings/firmware/
Dfsl,scu.yaml15 resource management. It exists on some i.MX8 processors. e.g. i.MX8QM
/Linux-v6.1/drivers/remoteproc/
Dimx_dsp_rproc.c269 /* Specific configuration for i.MX8QM */
736 * On i.MX8QM and i.MX8QXP there is multiple power domains
819 * For i.MX8QXP and i.MX8QM, DSP should be started and stopped by System
/Linux-v6.1/drivers/pinctrl/freescale/
Dpinctrl-imx8qm.c333 MODULE_DESCRIPTION("NXP i.MX8QM pinctrl driver");
/Linux-v6.1/sound/soc/fsl/
Dfsl_mqs.c200 * But in i.MX8QM/i.MX8QXP the control register is moved in fsl_mqs_probe()
Dfsl_asrc.c77 * i.MX8QM/i.MX8QXP uses the same map for input and output.
78 * clk_map_imx8qm[0] is for i.MX8QM asrc0
79 * clk_map_imx8qm[1] is for i.MX8QM asrc1
/Linux-v6.1/Documentation/devicetree/bindings/arm/
Dfsl.yaml1031 - description: i.MX8QM based Boards
1034 - fsl,imx8qm-mek # i.MX8QM MEK Board
/Linux-v6.1/drivers/net/ethernet/freescale/
Dfec.h498 /* i.MX8QM ENET IP version add new feture to generate delayed TXC/RXC