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/Linux-v6.6/drivers/firmware/xilinx/
DKconfig4 menu "Zynq MPSoC Firmware Drivers"
8 bool "Enable Xilinx Zynq MPSoC firmware interface"
20 bool "Enable Xilinx Zynq MPSoC firmware debug APIs"
Dzynqmp-debug.h3 * Xilinx Zynq MPSoC Firmware layer
Dzynqmp-debug.c3 * Xilinx Zynq MPSoC Firmware layer for debugfs APIs
/Linux-v6.6/Documentation/devicetree/bindings/reset/
Dxlnx,zynqmp-reset.yaml7 title: Zynq UltraScale+ MPSoC and Versal reset
13 The Zynq UltraScale+ MPSoC and Versal has several different resets.
24 For list of all valid reset indices for Zynq UltraScale+ MPSoC
/Linux-v6.6/drivers/soc/xilinx/
DKconfig5 bool "Enable Xilinx Zynq MPSoC Power Management driver"
20 bool "Enable Zynq MPSoC generic PM domains"
Dzynqmp_power.c3 * Xilinx Zynq MPSoC Power Management
/Linux-v6.6/Documentation/devicetree/bindings/fpga/
Dxlnx,zynqmp-pcap-fpga.yaml7 title: Xilinx Zynq Ultrascale MPSoC FPGA Manager
13 Device Tree Bindings for Zynq Ultrascale MPSoC FPGA Manager.
/Linux-v6.6/Documentation/devicetree/bindings/rtc/
Dxlnx,zynqmp-rtc.yaml7 title: Xilinx Zynq Ultrascale+ MPSoC Real Time Clock
10 RTC controller for the Xilinx Zynq MPSoC Real Time Clock.
/Linux-v6.6/Documentation/driver-api/xilinx/
Deemi.rst2 Xilinx Zynq MPSoC EEMI Documentation
5 Xilinx Zynq MPSoC Firmware Interface
/Linux-v6.6/drivers/clk/zynqmp/
DMakefile2 # Zynq Ultrascale+ MPSoC clock specific Makefile
Dclk-gate-zynqmp.c3 * Zynq UltraScale+ MPSoC clock controller
Dclk-mux-zynqmp.c3 * Zynq UltraScale+ MPSoC mux
Dclkc.c3 * Zynq UltraScale+ MPSoC clock controller
675 pr_err("Zynq Ultrascale+ MPSoC clk %s: register failed with %ld\n", in zynqmp_register_clocks()
Dpll.c3 * Zynq UltraScale+ MPSoC PLL driver
/Linux-v6.6/Documentation/devicetree/bindings/net/
Dcdns,macb.yaml24 - cdns,zynqmp-gem # Xilinx Zynq Ultrascale+ MPSoC
32 - xlnx,zynqmp-gem # Xilinx Zynq Ultrascale+ MPSoC
/Linux-v6.6/Documentation/devicetree/bindings/spi/
Dspi-zynqmp-qspi.yaml7 title: Xilinx Zynq UltraScale+ MPSoC GQSPI controller
/Linux-v6.6/Documentation/devicetree/bindings/serial/
Dcdns,uart.yaml19 - description: UART controller for Zynq Ultrascale+ MPSoC
/Linux-v6.6/Documentation/devicetree/bindings/nvmem/
Dxlnx,zynqmp-nvmem.txt2 = Zynq UltraScale+ MPSoC nvmem firmware driver binding =
/Linux-v6.6/Documentation/devicetree/bindings/power/reset/
Dxlnx,zynqmp-power.yaml7 title: Xilinx Zynq MPSoC Power Management
/Linux-v6.6/include/dt-bindings/clock/
Dxlnx-zynqmp-clk.h3 * Xilinx Zynq MPSoC Firmware layer
/Linux-v6.6/drivers/rtc/
Drtc-zynqmp.c3 * Xilinx Zynq Ultrascale+ MPSoC Real Time Clock Driver
395 MODULE_DESCRIPTION("Xilinx Zynq MPSoC RTC driver");
/Linux-v6.6/Documentation/devicetree/bindings/firmware/xilinx/
Dxlnx,zynqmp-firmware.yaml23 - description: For implementations complying for Zynq Ultrascale+ MPSoC.
/Linux-v6.6/Documentation/devicetree/bindings/arm/
Dxilinx.yaml13 Xilinx boards with Zynq-7000 SOC or Zynq UltraScale+ MPSoC
/Linux-v6.6/Documentation/devicetree/bindings/mailbox/
Dxlnx,zynqmp-ipi-mailbox.yaml11 messaging between two Xilinx Zynq UltraScale+ MPSoC IPI agents. Each IPI
/Linux-v6.6/Documentation/devicetree/bindings/display/xlnx/
Dxlnx,zynqmp-dpsub.yaml10 The DisplayPort subsystem of Xilinx ZynqMP (Zynq UltraScale+ MPSoC)

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