Searched full:mpsoc (Results 1 – 25 of 35) sorted by relevance
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| /Linux-v6.1/Documentation/devicetree/bindings/reset/ |
| D | xlnx,zynqmp-reset.txt | 2 = Zynq UltraScale+ MPSoC and Versal reset driver binding =
4 The Zynq UltraScale+ MPSoC and Versal has several different resets.
6 See Chapter 36 of the Zynq UltraScale+ MPSoC TRM (UG) for more information
13 - compatible: "xlnx,zynqmp-reset" for Zynq UltraScale+ MPSoC platform
41 For list of all valid reset indices for Zynq UltraScale+ MPSoC see
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| /Linux-v6.1/drivers/firmware/xilinx/ |
| D | Kconfig | 4 menu "Zynq MPSoC Firmware Drivers"
8 bool "Enable Xilinx Zynq MPSoC firmware interface"
20 bool "Enable Xilinx Zynq MPSoC firmware debug APIs"
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| D | zynqmp-debug.h | 3 * Xilinx Zynq MPSoC Firmware layer
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| D | zynqmp-debug.c | 3 * Xilinx Zynq MPSoC Firmware layer for debugfs APIs
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| /Linux-v6.1/Documentation/devicetree/bindings/clock/ |
| D | xlnx,zynqmp-clk.txt | 2 Device Tree Clock bindings for the Zynq Ultrascale+ MPSoC controlled using
3 Zynq MPSoC firmware interface
5 The clock controller is a h/w block of Zynq Ultrascale+ MPSoC clock
24 The Zynq UltraScale+ MPSoC has one primary and four alternative reference clock
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| /Linux-v6.1/drivers/soc/xilinx/ |
| D | Kconfig | 5 bool "Enable Xilinx Zynq MPSoC Power Management driver"
20 bool "Enable Zynq MPSoC generic PM domains"
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| /Linux-v6.1/Documentation/devicetree/bindings/fpga/ |
| D | xlnx,zynqmp-pcap-fpga.yaml | 7 title: Xilinx Zynq Ultrascale MPSoC FPGA Manager
13 Device Tree Bindings for Zynq Ultrascale MPSoC FPGA Manager.
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| /Linux-v6.1/Documentation/devicetree/bindings/power/ |
| D | xlnx,zynqmp-genpd.txt | 2 Device Tree Bindings for the Xilinx Zynq MPSoC PM domains
9 == Zynq MPSoC Generic PM Domain Node ==
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| /Linux-v6.1/Documentation/devicetree/bindings/rtc/ |
| D | xlnx,zynqmp-rtc.yaml | 7 title: Xilinx Zynq Ultrascale+ MPSoC Real Time Clock
10 RTC controller for the Xilinx Zynq MPSoC Real Time Clock.
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| /Linux-v6.1/Documentation/driver-api/xilinx/ |
| D | eemi.rst | 2 Xilinx Zynq MPSoC EEMI Documentation
5 Xilinx Zynq MPSoC Firmware Interface
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| /Linux-v6.1/drivers/clk/zynqmp/ |
| D | Makefile | 2 # Zynq Ultrascale+ MPSoC clock specific Makefile
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| D | clk-gate-zynqmp.c | 3 * Zynq UltraScale+ MPSoC clock controller
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| D | clk-mux-zynqmp.c | 3 * Zynq UltraScale+ MPSoC mux
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| D | clkc.c | 3 * Zynq UltraScale+ MPSoC clock controller
674 pr_err("Zynq Ultrascale+ MPSoC clk %s: register failed with %ld\n", in zynqmp_register_clocks()
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| /Linux-v6.1/Documentation/devicetree/bindings/net/ |
| D | cdns,macb.yaml | 24 - cdns,zynqmp-gem # Xilinx Zynq Ultrascale+ MPSoC
32 - xlnx,zynqmp-gem # Xilinx Zynq Ultrascale+ MPSoC
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| /Linux-v6.1/Documentation/devicetree/bindings/spi/ |
| D | spi-zynqmp-qspi.yaml | 7 title: Xilinx Zynq UltraScale+ MPSoC GQSPI controller
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| /Linux-v6.1/Documentation/devicetree/bindings/serial/ |
| D | cdns,uart.yaml | 22 - description: UART controller for Zynq Ultrascale+ MPSoC
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| /Linux-v6.1/Documentation/devicetree/bindings/nvmem/ |
| D | xlnx,zynqmp-nvmem.txt | 2 = Zynq UltraScale+ MPSoC nvmem firmware driver binding =
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| /Linux-v6.1/Documentation/devicetree/bindings/power/reset/ |
| D | xlnx,zynqmp-power.yaml | 7 title: Xilinx Zynq MPSoC Power Management Device Tree Bindings
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| /Linux-v6.1/include/dt-bindings/clock/ |
| D | xlnx-zynqmp-clk.h | 3 * Xilinx Zynq MPSoC Firmware layer
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| /Linux-v6.1/Documentation/devicetree/bindings/firmware/xilinx/ |
| D | xlnx,zynqmp-firmware.yaml | 23 - description: For implementations complying for Zynq Ultrascale+ MPSoC.
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| /Linux-v6.1/drivers/rtc/ |
| D | rtc-zynqmp.c | 3 * Xilinx Zynq Ultrascale+ MPSoC Real Time Clock Driver
397 MODULE_DESCRIPTION("Xilinx Zynq MPSoC RTC driver");
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| /Linux-v6.1/Documentation/devicetree/bindings/arm/ |
| D | xilinx.yaml | 13 Xilinx boards with Zynq-7000 SOC or Zynq UltraScale+ MPSoC
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| /Linux-v6.1/Documentation/devicetree/bindings/mailbox/ |
| D | xlnx,zynqmp-ipi-mailbox.yaml | 11 messaging between two Xilinx Zynq UltraScale+ MPSoC IPI agents. Each IPI
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| /Linux-v6.1/Documentation/devicetree/bindings/display/xlnx/ |
| D | xlnx,zynqmp-dpsub.yaml | 10 The DisplayPort subsystem of Xilinx ZynqMP (Zynq UltraScale+ MPSoC)
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