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/Linux-v6.1/drivers/staging/greybus/
DKconfig1 # SPDX-License-Identifier: GPL-2.0
11 To compile this code as a module, chose M here: the module
12 will be called gb-audio.ko
20 bridge from an APB-I2S port to a Unipro network.
22 To compile this code as a module, chose M here: the module
23 will be called gb-audio-codec.ko
32 To compile this code as a module, chose M here: the module
33 will be called gb-bootrom.ko
42 To compile this code as a module, chose M here: the module
43 will be called gb-camera.ko
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/Linux-v6.1/Documentation/devicetree/bindings/phy/
Dmediatek,ufs-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/phy/mediatek,ufs-phy.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: MediaTek Universal Flash Storage (UFS) M-PHY binding
11 - Stanley Chu <stanley.chu@mediatek.com>
12 - Chunfeng Yun <chunfeng.yun@mediatek.com>
15 UFS M-PHY nodes are defined to describe on-chip UFS M-PHY hardware macro.
16 Each UFS M-PHY node should have its own node.
17 To bind UFS M-PHY with UFS host controller, the controller node should
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Dphy-rockchip-inno-usb2.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/phy/phy-rockchip-inno-usb2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip USB2.0 phy with inno IP block
10 - Heiko Stuebner <heiko@sntech.de>
15 - rockchip,px30-usb2phy
16 - rockchip,rk3128-usb2phy
17 - rockchip,rk3228-usb2phy
18 - rockchip,rk3308-usb2phy
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Drockchip-dp-phy.txt1 Rockchip specific extensions to the Analogix Display Port PHY
2 ------------------------------------
5 - compatible : should be one of the following supported values:
6 - "rockchip.rk3288-dp-phy"
7 - clocks: from common clock binding: handle to dp clock.
9 - clock-names: from common clock binding:
10 Required elements: "24m"
11 - #phy-cells : from the generic PHY bindings, must be 0;
16 compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd";
20 edp_phy: edp-phy {
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/Linux-v6.1/drivers/char/tpm/
Dtpm_tis_spi_main.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * Christophe Ricard <christophe-h.ricard@st.com>
10 * Maintained by: <tpmdd-devel@lists.sourceforge.net>
46 * [1] https://trustedcomputinggroup.org/resource/pc-client-platform-tpm-profile-ptp-specification/
48 static int tpm_tis_spi_flow_control(struct tpm_tis_spi_phy *phy, in tpm_tis_spi_flow_control() argument
51 struct spi_message m; in tpm_tis_spi_flow_control() local
54 if ((phy->iobuf[3] & 0x01) == 0) { in tpm_tis_spi_flow_control()
57 spi_xfer->len = 1; in tpm_tis_spi_flow_control()
58 spi_message_init(&m); in tpm_tis_spi_flow_control()
59 spi_message_add_tail(spi_xfer, &m); in tpm_tis_spi_flow_control()
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Dtpm_tis_spi_cr50.c1 // SPDX-License-Identifier: GPL-2.0
23 * - can go to sleep not earlier than after CR50_SLEEP_DELAY_MSEC.
24 * - needs up to CR50_WAKE_START_DELAY_USEC to wake after sleep.
25 * - requires waiting for "ready" IRQ, if supported; or waiting for at least
27 * - waits for up to CR50_FLOW_CONTROL for flow control 'ready' indication.
55 static inline struct cr50_spi_phy *to_cr50_spi_phy(struct tpm_tis_spi_phy *phy) in to_cr50_spi_phy() argument
57 return container_of(phy, struct cr50_spi_phy, spi_phy); in to_cr50_spi_phy()
69 cr50_phy->irq_confirmed = true; in cr50_spi_irq_handler()
70 complete(&cr50_phy->spi_phy.ready); in cr50_spi_irq_handler()
79 static void cr50_ensure_access_delay(struct cr50_spi_phy *phy) in cr50_ensure_access_delay() argument
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/Linux-v6.1/drivers/usb/phy/
DKconfig1 # SPDX-License-Identifier: GPL-2.0
26 depends on USB_GADGET || !USB_GADGET # if USB_GADGET=m, this can't be 'y'
36 depends on USB_GADGET || !USB_GADGET # if USB_GADGET=m, this can't be 'y'
40 USB-On-The-Go transceiver working with the OMAP OTG controller.
46 will be called phy-isp1301-omap.
49 tristate "Keystone USB PHY Driver"
53 Enable this to support Keystone USB phy. This driver provides
54 interface to interact with USB 2.0 and USB 3.0 PHY that is part
59 depends on USB_GADGET || !USB_GADGET # if USB_GADGET=m, NOP can't be built-in
63 built-in with usb ip or which are autonomous and doesn't require any
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/Linux-v6.1/drivers/phy/marvell/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # Phy drivers for Marvell platforms
6 bool "Armada 375 USB cluster PHY support" if COMPILE_TEST
12 tristate "Marvell Berlin SATA PHY driver"
17 Enable this to support the SATA PHY on Marvell Berlin SoCs.
20 tristate "Marvell Berlin USB PHY Driver"
25 Enable this to support the USB PHY on Marvell Berlin SoCs.
46 Enable this to support Marvell A3700 UTMI PHY driver.
76 Enable this to support Marvell CP110 UTMI PHY driver.
85 tristate "Marvell USB HSIC 28nm PHY Driver"
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/Linux-v6.1/drivers/phy/hisilicon/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # Phy drivers for Hisilicon platforms
6 tristate "hi6220 USB PHY support"
12 Enable this to support the HISILICON HI6220 USB PHY.
14 To compile this driver as a module, choose M here.
17 tristate "hi3660 USB PHY support"
22 Enable this to support the HISILICON HI3660 USB PHY.
24 To compile this driver as a module, choose M here.
27 tristate "hi3670 USB PHY support"
32 Enable this to support the HISILICON HI3670 USB PHY.
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/Linux-v6.1/drivers/phy/freescale/
Dphy-fsl-imx8qm-lvds-phy.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2017-2020,2022 NXP
12 #include <linux/phy/phy.h>
23 #define M(n) FIELD_PREP(M_MASK, (n)) macro
36 #define CTRL_RESET_VAL (M(0x0) | CCM(0x4) | CA(0x4) | TST(0x25))
38 /* PHY initialization value and mask */
40 #define CTRL_INIT_VAL (M(0x0) | CCM(0x5) | CA(0x4) | TST(0x25) | RFB)
54 struct phy *phy; member
66 static int mixel_lvds_phy_init(struct phy *phy) in mixel_lvds_phy_init() argument
68 struct mixel_lvds_phy_priv *priv = dev_get_drvdata(phy->dev.parent); in mixel_lvds_phy_init()
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/Linux-v6.1/drivers/gpu/drm/sun4i/
Dsun8i_hdmi_phy_clk.c1 // SPDX-License-Identifier: GPL-2.0+
6 #include <linux/clk-provider.h>
12 struct sun8i_hdmi_phy *phy; member
23 unsigned long rate = req->rate; in sun8i_phy_clk_determine_rate()
49 abs(rate - rounded / i) < in sun8i_phy_clk_determine_rate()
50 abs(rate - best_rate / best_div)) { in sun8i_phy_clk_determine_rate()
61 req->rate = best_rate / best_div; in sun8i_phy_clk_determine_rate()
62 req->best_parent_rate = best_rate; in sun8i_phy_clk_determine_rate()
63 req->best_parent_hw = best_parent; in sun8i_phy_clk_determine_rate()
74 regmap_read(priv->phy->regs, SUN8I_HDMI_PHY_PLL_CFG2_REG, &reg); in sun8i_phy_clk_recalc_rate()
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/Linux-v6.1/drivers/phy/mediatek/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # Phy drivers for Mediatek devices
6 tristate "MediaTek PCIe-PHY Driver"
11 Say 'Y' here to add support for MediaTek PCIe PHY driver.
12 This driver create the basic PHY instance and provides initialize
17 tristate "MediaTek T-PHY Driver"
23 Say 'Y' here to add support for MediaTek T-PHY driver,
25 SATA, and meanwhile supports two version T-PHY which have
26 different banks layout, the T-PHY with shared banks between
27 multi-ports is first version, otherwise is second version,
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/Linux-v6.1/drivers/phy/intel/
DKconfig1 # SPDX-License-Identifier: GPL-2.0
3 # Phy drivers for Intel platforms
6 tristate "Intel Keem Bay EMMC PHY driver"
14 To compile this driver as a module, choose M here: the module
15 will be called phy-keembay-emmc.ko.
18 tristate "Intel Keem Bay USB PHY driver"
26 To compile this driver as a module, choose M here: the module
27 will be called phy-keembay-usb.ko.
44 tristate "Intel Lightning Mountain EMMC PHY driver"
48 Enable this to support the Intel EMMC PHY
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/Linux-v6.1/drivers/phy/qualcomm/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # Phy drivers for Qualcomm and Atheros platforms
6 tristate "Atheros AR71XX/9XXX USB PHY driver"
12 Enable this to support the USB PHY on Atheros AR71XX/9XXX SoCs.
15 tristate "Qualcomm APQ8064 SATA SerDes/PHY driver"
22 tristate "Qualcomm eDP PHY driver"
28 Enable this driver to support the Qualcomm eDP PHY found in various
32 tristate "Qualcomm IPQ4019 USB PHY driver"
36 Support for the USB PHY-s on Qualcomm IPQ40xx SoC-s.
39 tristate "Qualcomm IPQ806x SATA SerDes/PHY driver"
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/Linux-v6.1/Documentation/devicetree/bindings/net/
Dnvidia,tegra234-mgbe.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/nvidia,tegra234-mgbe.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Tegra234 MGBE Multi-Gigabit Ethernet Controller
10 - Thierry Reding <treding@nvidia.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 const: nvidia,tegra234-mgbe
20 reg-names:
22 - const: hypervisor
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Dsunplus,sp7021-emac.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/net/sunplus,sp7021-emac.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Wells Lu <wellslutw@gmail.com>
14 Sunplus SP7021 dual 10M/100M Ethernet MAC controller.
19 const: sunplus,sp7021-emac
33 ethernet-ports:
36 description: Ethernet ports to PHY
39 "#address-cells":
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/Linux-v6.1/drivers/net/fddi/skfp/
Dsmt.c1 // SPDX-License-Identifier: GPL-2.0-or-later
26 #define m_fc(mb) ((mb)->sm_data[0])
55 static int phy_index(struct s_smc *smc, int phy);
57 static int phy_con_resource_index(struct s_smc *smc, int phy);
82 static void smt_fill_lem(struct s_smc *smc, struct smt_p_lem *lem, int phy);
111 return(*(short *)(&addr->a[0]) == in is_my_addr()
112 *(short *)(&smc->mib.m[MAC0].fddiMACSMTAddress.a[0]) in is_my_addr()
113 && *(short *)(&addr->a[2]) == in is_my_addr()
114 *(short *)(&smc->mib.m[MAC0].fddiMACSMTAddress.a[2]) in is_my_addr()
115 && *(short *)(&addr->a[4]) == in is_my_addr()
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/Linux-v6.1/drivers/phy/microchip/
Dlan966x_serdes.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 #include <linux/phy.h>
8 #include <linux/phy/phy.h>
11 #include <dt-bindings/phy/phy-lan966x-serdes.h>
38 #define SERDES_MUX_GMII(i, p, m, c) \ argument
39 SERDES_MUX(i, p, PHY_MODE_ETHERNET, PHY_INTERFACE_MODE_GMII, m, c)
40 #define SERDES_MUX_SGMII(i, p, m, c) \ argument
41 SERDES_MUX(i, p, PHY_MODE_ETHERNET, PHY_INTERFACE_MODE_SGMII, m, c)
42 #define SERDES_MUX_QSGMII(i, p, m, c) \ argument
43 SERDES_MUX(i, p, PHY_MODE_ETHERNET, PHY_INTERFACE_MODE_QSGMII, m, c)
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/Linux-v6.1/drivers/scsi/bfa/
Dbfa_ioc.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2005-2014 Brocade Communications Systems, Inc.
4 * Copyright (c) 2014- QLogic Corporation.
8 * Linux driver for QLogic BR-series Fibre Channel Host Bus Adapter.
31 bfa_timer_begin((__ioc)->timer_mod, &(__ioc)->ioc_timer, \
33 #define bfa_ioc_timer_stop(__ioc) bfa_timer_stop(&(__ioc)->ioc_timer)
36 bfa_timer_begin((__ioc)->timer_mod, &(__ioc)->hb_timer, \
38 #define bfa_hb_timer_stop(__ioc) bfa_timer_stop(&(__ioc)->hb_timer)
55 ((__ioc)->ioc_hwif->ioc_firmware_lock(__ioc))
57 ((__ioc)->ioc_hwif->ioc_firmware_unlock(__ioc))
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/Linux-v6.1/drivers/net/ethernet/wiznet/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
27 PHY and hardware TCP/IP stack, but this driver is limited to
28 the MAC and PHY functions only, onchip TCP/IP is unused.
30 To compile this driver as a module, choose M here: the module
40 PHY and hardware TCP/IP stack, but this driver is limited to
41 the MAC and PHY functions only, onchip TCP/IP is unused.
43 To compile this driver as a module, choose M here: the module
55 after mapping to Memory-Mapped I/O space.
62 which are directly mapped to Memory-Mapped I/O space.
84 To compile this driver as a module, choose M here: the module
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/Linux-v6.1/drivers/phy/rockchip/
Dphy-rockchip-dp.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Rockchip DP PHY driver
6 * Author: Yakir Yang <ykk@@rock-chips.com>
13 #include <linux/phy/phy.h>
32 static int rockchip_set_phy_state(struct phy *phy, bool enable) in rockchip_set_phy_state() argument
34 struct rockchip_dp_phy *dp = phy_get_drvdata(phy); in rockchip_set_phy_state()
38 ret = regmap_write(dp->grf, GRF_SOC_CON12, in rockchip_set_phy_state()
42 dev_err(dp->dev, "Can't enable PHY power %d\n", ret); in rockchip_set_phy_state()
46 ret = clk_prepare_enable(dp->phy_24m); in rockchip_set_phy_state()
48 clk_disable_unprepare(dp->phy_24m); in rockchip_set_phy_state()
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/Linux-v6.1/drivers/net/wireless/mediatek/mt76/mt7921/
Ddebugfs.c1 // SPDX-License-Identifier: ISC
13 mt76_wr(dev, dev->mt76.debugfs_reg, val); in mt7921_reg_set()
25 *val = mt76_rr(dev, dev->mt76.debugfs_reg); in mt7921_reg_get()
40 dev->fw_debug = (u8)val; in mt7921_fw_debug_set()
41 mt7921_mcu_fw_log_2_host(dev, dev->fw_debug); in mt7921_fw_debug_set()
53 *val = dev->fw_debug; in mt7921_fw_debug_get()
62 mt7921_ampdu_stat_read_phy(struct mt7921_phy *phy, in mt7921_ampdu_stat_read_phy() argument
65 struct mt7921_dev *dev = file->private; in mt7921_ampdu_stat_read_phy()
68 if (!phy) in mt7921_ampdu_stat_read_phy()
71 mt7921_mac_update_mib_stats(phy); in mt7921_ampdu_stat_read_phy()
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/Linux-v6.1/drivers/gpio/
Dgpio-stp-xway.c1 // SPDX-License-Identifier: GPL-2.0-only
74 #define xway_stp_r32(m, reg) __raw_readl(m + reg) argument
75 #define xway_stp_w32(m, val, reg) __raw_writel(val, m + reg) argument
76 #define xway_stp_w32_mask(m, clear, set, reg) \ argument
77 xway_stp_w32(m, (xway_stp_r32(m, reg) & ~(clear)) | (set), reg)
84 u8 groups; /* we can drive 1-3 groups of 8bit each */
94 * xway_stp_get() - gpio_chip->get - get gpios.
104 return (xway_stp_r32(chip->virt, XWAY_STP_CPU0) & BIT(gpio)); in xway_stp_get()
108 * xway_stp_set() - gpio_chip->set - set gpios.
120 chip->shadow |= BIT(gpio); in xway_stp_set()
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/Linux-v6.1/drivers/usb/common/
DKconfig1 # SPDX-License-Identifier: GPL-2.0
13 Say Y here if you are working on a system with led-class supported
18 tristate "USB ULPI PHY interface support"
22 USB 2.0 PHY interface. The ULPI specification defines a standard set
28 controllers which support ULPI register access and have ULPI PHY
29 attached to them. The ULPI PHY drivers themselves are normal PHY
35 To compile this driver as a module, choose M here: the module will
50 To compile the driver as a module, choose M here: the module will
51 be called usb-conn-gpio.ko
/Linux-v6.1/drivers/media/platform/ti/cal/
Dcal_regs.h1 /* SPDX-License-Identifier: GPL-2.0-only */
20 * LDOs on the device are disabled if CSI-2 module is powered on
25 * Errata does not apply when CSI-2 module is powered off
43 #define CAL_HL_IRQSTATUS_RAW(m) (0x20U + (m) * 0x10U) argument
44 #define CAL_HL_IRQSTATUS(m) (0x24U + (m) * 0x10U) argument
45 #define CAL_HL_IRQENABLE_SET(m) (0x28U + (m) * 0x10U) argument
46 #define CAL_HL_IRQENABLE_CLR(m) (0x2cU + (m) * 0x10U) argument
47 #define CAL_PIX_PROC(m) (0xc0U + (m) * 0x4U) argument
63 #define CAL_WR_DMA_CTRL(m) (0x200U + (m) * 0x10U) argument
64 #define CAL_WR_DMA_ADDR(m) (0x204U + (m) * 0x10U) argument
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