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/Linux-v6.1/drivers/phy/freescale/
Dphy-fsl-lynx-28g.c23 #define LYNX_28G_LNa_PCC_OFFSET(lane) (4 * (LYNX_28G_NUM_LANE - (lane->id) - 1)) argument
44 /* Per SerDes lane registers */
45 /* Lane a General Control Register */
46 #define LYNX_28G_LNaGCR0(lane) (0x800 + (lane) * 0x100 + 0x0) argument
54 /* Lane a Tx Reset Control Register */
55 #define LYNX_28G_LNaTRSTCTL(lane) (0x800 + (lane) * 0x100 + 0x20) argument
60 /* Lane a Tx General Control Register */
61 #define LYNX_28G_LNaTGCR0(lane) (0x800 + (lane) * 0x100 + 0x24) argument
70 #define LYNX_28G_LNaTECR0(lane) (0x800 + (lane) * 0x100 + 0x30) argument
72 /* Lane a Rx Reset Control Register */
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/Linux-v6.1/drivers/phy/marvell/
Dphy-mvebu-cp110-comphy.c128 * A lane is described by the following bitfields:
181 unsigned lane; member
189 .lane = _lane, \
199 .lane = _lane, \
208 /* lane 0 */
213 /* lane 1 */
220 /* lane 2 */
229 /* lane 3 */
236 /* lane 4 */
249 /* lane 5 */
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Dphy-mvebu-a3700-comphy.c39 * When accessing common PHY lane registers directly, we need to shift by 1,
174 * This register is not from PHY lane register space. It only exists in the
175 * indirect register space, before the actual PHY lane 2 registers. So the
183 #define COMPHY_PHY_REG(lane, reg) (((1 - (lane)) * 0x28) + ((reg) & 0x3f)) argument
226 unsigned int lane; member
233 .lane = _lane, \
245 /* lane 0 */
250 /* lane 1 */
255 /* lane 2 */
386 /* Used for accessing lane 2 registers (SATA/USB3 PHY) */
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Dphy-armada38x-comphy.c46 struct a38x_comphy_lane lane[MAX_A38X_COMPHY]; member
58 static void a38x_set_conf(struct a38x_comphy_lane *lane, bool enable) in a38x_set_conf() argument
60 struct a38x_comphy *priv = lane->priv; in a38x_set_conf()
66 conf |= BIT(lane->port); in a38x_set_conf()
68 conf &= ~BIT(lane->port); in a38x_set_conf()
73 static void a38x_comphy_set_reg(struct a38x_comphy_lane *lane, in a38x_comphy_set_reg() argument
78 val = readl_relaxed(lane->base + offset) & ~mask; in a38x_comphy_set_reg()
79 writel(val | value, lane->base + offset); in a38x_comphy_set_reg()
82 static void a38x_comphy_set_speed(struct a38x_comphy_lane *lane, in a38x_comphy_set_speed() argument
85 a38x_comphy_set_reg(lane, COMPHY_CFG1, in a38x_comphy_set_speed()
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/Linux-v6.1/drivers/net/dsa/b53/
Db53_serdes.c42 static void b53_serdes_set_lane(struct b53_device *dev, u8 lane) in b53_serdes_set_lane() argument
44 if (dev->serdes_lane == lane) in b53_serdes_set_lane()
47 WARN_ON(lane > 1); in b53_serdes_set_lane()
50 SERDES_XGXSBLK0_BLOCKADDRESS, lane); in b53_serdes_set_lane()
51 dev->serdes_lane = lane; in b53_serdes_set_lane()
54 static void b53_serdes_write(struct b53_device *dev, u8 lane, in b53_serdes_write() argument
57 b53_serdes_set_lane(dev, lane); in b53_serdes_write()
61 static u16 b53_serdes_read(struct b53_device *dev, u8 lane, in b53_serdes_read() argument
64 b53_serdes_set_lane(dev, lane); in b53_serdes_read()
74 u8 lane = pcs_to_b53_pcs(pcs)->lane; in b53_serdes_config() local
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/Linux-v6.1/drivers/net/dsa/mv88e6xxx/
Dserdes.c37 int lane, int device, int reg, u16 *val) in mv88e6390_serdes_read() argument
41 return mv88e6xxx_phy_read(chip, lane, reg_c45, val); in mv88e6390_serdes_read()
45 int lane, int device, int reg, u16 val) in mv88e6390_serdes_write() argument
49 return mv88e6xxx_phy_write(chip, lane, reg_c45, val); in mv88e6390_serdes_write()
124 int mv88e6352_serdes_power(struct mv88e6xxx_chip *chip, int port, int lane, in mv88e6352_serdes_power() argument
146 int lane, unsigned int mode, in mv88e6352_serdes_pcs_config() argument
195 int lane, struct phylink_link_state *state) in mv88e6352_serdes_pcs_get_state() argument
222 int lane) in mv88e6352_serdes_pcs_an_restart() argument
235 int lane, int speed, int duplex) in mv88e6352_serdes_pcs_link_up() argument
268 int lane = -ENODEV; in mv88e6352_serdes_get_lane() local
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Dserdes.h113 int lane, unsigned int mode,
117 int lane, unsigned int mode,
121 int lane, struct phylink_link_state *state);
123 int lane, struct phylink_link_state *state);
125 int lane, struct phylink_link_state *state);
127 int lane, struct phylink_link_state *state);
129 int lane);
131 int lane);
133 int lane, int speed, int duplex);
135 int lane, int speed, int duplex);
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/Linux-v6.1/drivers/phy/tegra/
Dxusb.c109 int tegra_xusb_lane_parse_dt(struct tegra_xusb_lane *lane, in tegra_xusb_lane_parse_dt() argument
112 struct device *dev = &lane->pad->dev; in tegra_xusb_lane_parse_dt()
120 err = match_string(lane->soc->funcs, lane->soc->num_funcs, function); in tegra_xusb_lane_parse_dt()
122 dev_err(dev, "invalid function \"%s\" for lane \"%pOFn\"\n", in tegra_xusb_lane_parse_dt()
127 lane->function = err; in tegra_xusb_lane_parse_dt()
135 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); in tegra_xusb_lane_destroy() local
137 lane->pad->ops->remove(lane); in tegra_xusb_lane_destroy()
185 struct phy *lane; in tegra_xusb_pad_register() local
193 pad->lanes = devm_kcalloc(&pad->dev, pad->soc->num_lanes, sizeof(lane), in tegra_xusb_pad_register()
202 struct tegra_xusb_lane *lane; in tegra_xusb_pad_register() local
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Dxusb-tegra124.c292 struct tegra_xusb_lane *lane; in tegra124_usb3_save_context() local
300 lane = port->base.lane; in tegra124_usb3_save_context()
302 if (lane->pad == padctl->pcie) in tegra124_usb3_save_context()
303 offset = XUSB_PADCTL_IOPHY_MISC_PAD_PX_CTL6(lane->index); in tegra124_usb3_save_context()
452 static void tegra124_usb2_lane_remove(struct tegra_xusb_lane *lane) in tegra124_usb2_lane_remove() argument
454 struct tegra_xusb_usb2_lane *usb2 = to_usb2_lane(lane); in tegra124_usb2_lane_remove()
466 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); in tegra124_usb2_phy_init() local
468 return tegra124_xusb_padctl_enable(lane->pad->padctl); in tegra124_usb2_phy_init()
473 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); in tegra124_usb2_phy_exit() local
475 return tegra124_xusb_padctl_disable(lane->pad->padctl); in tegra124_usb2_phy_exit()
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Dxusb-tegra210.c447 static int tegra210_usb3_lane_map(struct tegra_xusb_lane *lane) in tegra210_usb3_lane_map() argument
452 if (map->index == lane->index && in tegra210_usb3_lane_map()
453 strcmp(map->type, lane->pad->soc->name) == 0) { in tegra210_usb3_lane_map()
454 dev_dbg(lane->pad->padctl->dev, "lane = %s map to port = usb3-%d\n", in tegra210_usb3_lane_map()
455 lane->pad->soc->lanes[lane->index].name, map->port); in tegra210_usb3_lane_map()
706 struct tegra_xusb_lane *lane = tegra_xusb_find_lane(padctl, "sata", 0); in tegra210_sata_uphy_enable() local
716 if (IS_ERR(lane)) in tegra210_sata_uphy_enable()
722 usb = tegra_xusb_lane_check(lane, "usb3-ss"); in tegra210_sata_uphy_enable()
1058 static int tegra210_usb3_enable_phy_sleepwalk(struct tegra_xusb_lane *lane, in tegra210_usb3_enable_phy_sleepwalk() argument
1061 struct tegra_xusb_padctl *padctl = lane->pad->padctl; in tegra210_usb3_enable_phy_sleepwalk()
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Dxusb.h54 int tegra_xusb_lane_parse_dt(struct tegra_xusb_lane *lane,
62 to_usb3_lane(struct tegra_xusb_lane *lane) in to_usb3_lane() argument
64 return container_of(lane, struct tegra_xusb_usb3_lane, base); in to_usb3_lane()
75 to_usb2_lane(struct tegra_xusb_lane *lane) in to_usb2_lane() argument
77 return container_of(lane, struct tegra_xusb_usb2_lane, base); in to_usb2_lane()
85 to_ulpi_lane(struct tegra_xusb_lane *lane) in to_ulpi_lane() argument
87 return container_of(lane, struct tegra_xusb_ulpi_lane, base); in to_ulpi_lane()
104 to_hsic_lane(struct tegra_xusb_lane *lane) in to_hsic_lane() argument
106 return container_of(lane, struct tegra_xusb_hsic_lane, base); in to_hsic_lane()
114 to_pcie_lane(struct tegra_xusb_lane *lane) in to_pcie_lane() argument
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Dxusb-tegra186.c308 static void tegra186_usb2_lane_remove(struct tegra_xusb_lane *lane) in tegra186_usb2_lane_remove() argument
310 struct tegra_xusb_usb2_lane *usb2 = to_usb2_lane(lane); in tegra186_usb2_lane_remove()
315 static int tegra186_utmi_enable_phy_sleepwalk(struct tegra_xusb_lane *lane, in tegra186_utmi_enable_phy_sleepwalk() argument
318 struct tegra_xusb_padctl *padctl = lane->pad->padctl; in tegra186_utmi_enable_phy_sleepwalk()
320 unsigned int index = lane->index; in tegra186_utmi_enable_phy_sleepwalk()
460 static int tegra186_utmi_disable_phy_sleepwalk(struct tegra_xusb_lane *lane) in tegra186_utmi_disable_phy_sleepwalk() argument
462 struct tegra_xusb_padctl *padctl = lane->pad->padctl; in tegra186_utmi_disable_phy_sleepwalk()
464 unsigned int index = lane->index; in tegra186_utmi_disable_phy_sleepwalk()
501 static int tegra186_utmi_enable_phy_wake(struct tegra_xusb_lane *lane) in tegra186_utmi_enable_phy_wake() argument
503 struct tegra_xusb_padctl *padctl = lane->pad->padctl; in tegra186_utmi_enable_phy_wake()
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/Linux-v6.1/drivers/phy/
Dphy-xgene.c267 /* PHY lane CSR accessing from SDS indirectly */
519 u32 speed[MAX_LANE]; /* Index for override parameter per lane */
657 static void serdes_wr(struct xgene_phy_ctx *ctx, int lane, u32 reg, u32 data) in serdes_wr() argument
663 reg += lane * SERDES_LANE_STRIDE; in serdes_wr()
672 static void serdes_rd(struct xgene_phy_ctx *ctx, int lane, u32 reg, u32 *data) in serdes_rd() argument
677 reg += lane * SERDES_LANE_STRIDE; in serdes_rd()
683 static void serdes_clrbits(struct xgene_phy_ctx *ctx, int lane, u32 reg, in serdes_clrbits() argument
688 serdes_rd(ctx, lane, reg, &val); in serdes_clrbits()
690 serdes_wr(ctx, lane, reg, val); in serdes_clrbits()
693 static void serdes_setbits(struct xgene_phy_ctx *ctx, int lane, u32 reg, in serdes_setbits() argument
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/Linux-v6.1/Documentation/devicetree/bindings/media/
Dvideo-interfaces.yaml163 # Assume up to 9 physical lane indices
166 An array of physical data lane indexes. Position of an entry determines
167 the logical lane number, while the value of an entry indicates physical
168 lane, e.g. for 2-lane MIPI CSI-2 bus we could have "data-lanes = <1 2>;",
169 assuming the clock lane is on hardware lane 0. If the hardware does not
170 support lane reordering, monotonically incremented values shall be used
172 lane. This property is valid for serial busses only (e.g. MIPI CSI-2).
176 # Assume up to 9 physical lane indices
179 Physical clock lane index. Position of an entry determines the logical
180 lane number, while the value of an entry indicates physical lane, e.g. for
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/Linux-v6.1/sound/soc/tegra/
Dtegra186_asrc.c110 if (asrc->lane[id].ratio_source != in tegra186_asrc_runtime_resume()
117 asrc->lane[id].int_part); in tegra186_asrc_runtime_resume()
122 asrc->lane[id].frac_part); in tegra186_asrc_runtime_resume()
174 asrc->lane[id].input_thresh); in tegra186_asrc_in_hw_params()
197 asrc->lane[id].output_thresh); in tegra186_asrc_out_hw_params()
207 if (asrc->lane[id].hwcomp_disable) { in tegra186_asrc_out_hw_params()
226 1, asrc->lane[id].ratio_source); in tegra186_asrc_out_hw_params()
228 if (asrc->lane[id].ratio_source == TEGRA186_ASRC_RATIO_SOURCE_SW) { in tegra186_asrc_out_hw_params()
231 asrc->lane[id].int_part); in tegra186_asrc_out_hw_params()
234 asrc->lane[id].frac_part); in tegra186_asrc_out_hw_params()
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/Linux-v6.1/drivers/thunderbolt/
Dlc.c52 u32 ctrl, lane; in tb_lc_set_port_configured() local
66 /* Resolve correct lane */ in tb_lc_set_port_configured()
68 lane = TB_LC_SX_CTRL_L1C; in tb_lc_set_port_configured()
70 lane = TB_LC_SX_CTRL_L2C; in tb_lc_set_port_configured()
73 ctrl |= lane; in tb_lc_set_port_configured()
77 ctrl &= ~lane; in tb_lc_set_port_configured()
110 u32 ctrl, lane; in tb_lc_set_xdomain_configured() local
124 /* Resolve correct lane */ in tb_lc_set_xdomain_configured()
126 lane = TB_LC_SX_CTRL_L1D; in tb_lc_set_xdomain_configured()
128 lane = TB_LC_SX_CTRL_L2D; in tb_lc_set_xdomain_configured()
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/Linux-v6.1/drivers/gpu/drm/bridge/analogix/
Danalogix_dp_core.c239 int pre_emphasis, int lane) in analogix_dp_set_lane_lane_pre_emphasis() argument
241 switch (lane) { in analogix_dp_set_lane_lane_pre_emphasis()
262 int lane, lane_count, pll_tries, retval; in analogix_dp_link_start() local
269 for (lane = 0; lane < lane_count; lane++) in analogix_dp_link_start()
270 dp->link_train.cr_loop[lane] = 0; in analogix_dp_link_start()
290 for (lane = 0; lane < lane_count; lane++) in analogix_dp_link_start()
292 PRE_EMPHASIS_LEVEL_0, lane); in analogix_dp_link_start()
316 for (lane = 0; lane < lane_count; lane++) in analogix_dp_link_start()
317 buf[lane] = DP_TRAIN_PRE_EMPH_LEVEL_0 | in analogix_dp_link_start()
328 static unsigned char analogix_dp_get_lane_status(u8 link_status[2], int lane) in analogix_dp_get_lane_status() argument
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/Linux-v6.1/drivers/phy/xilinx/
Dphy-zynqmp.c29 * Lane Registers
152 #define XPSGTR_TYPE_SATA_0 2 /* SATA controller lane 0 */
153 #define XPSGTR_TYPE_SATA_1 3 /* SATA controller lane 1 */
154 #define XPSGTR_TYPE_PCIE_0 4 /* PCIe controller lane 0 */
155 #define XPSGTR_TYPE_PCIE_1 5 /* PCIe controller lane 1 */
156 #define XPSGTR_TYPE_PCIE_2 6 /* PCIe controller lane 2 */
157 #define XPSGTR_TYPE_PCIE_3 7 /* PCIe controller lane 3 */
158 #define XPSGTR_TYPE_DP_0 8 /* Display Port controller lane 0 */
159 #define XPSGTR_TYPE_DP_1 9 /* Display Port controller lane 1 */
171 * struct xpsgtr_ssc - structure to hold SSC settings for a lane
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/Linux-v6.1/Documentation/devicetree/bindings/media/i2c/
Dst,st-mipid02.txt6 CSI-2 first input port is a dual lane 800Mbps per lane whereas CSI-2 second
7 input port is a single lane 800Mbps. Both ports support clock and data lane
8 polarity swap. First port also supports data lane swap.
37 - data-lanes: shall be <1> for Port 1. for Port 0 dual-lane operation shall be
38 <1 2> or <2 1>. For Port 0 single-lane operation shall be <1> or <2>.
40 - lane-polarities: any lane can be inverted or not.
/Linux-v6.1/drivers/phy/mediatek/
Dphy-mtk-pcie.c36 * struct mtk_pcie_lane_efuse - eFuse data for each lane
40 * @lane_efuse_supported: software eFuse data is supported for this lane
51 * @num_lanes: supported lane numbers
67 * @efuse: pointer to eFuse data for each lane
81 unsigned int lane) in mtk_pcie_efuse_set_lane() argument
83 struct mtk_pcie_lane_efuse *data = &pcie_phy->efuse[lane]; in mtk_pcie_efuse_set_lane()
90 lane * PEXTP_ANA_LANE_OFFSET; in mtk_pcie_efuse_set_lane()
134 unsigned int lane) in mtk_pcie_efuse_read_for_lane() argument
136 struct mtk_pcie_lane_efuse *efuse = &pcie_phy->efuse[lane]; in mtk_pcie_efuse_read_for_lane()
141 snprintf(efuse_id, sizeof(efuse_id), "tx_ln%d_pmos", lane); in mtk_pcie_efuse_read_for_lane()
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/Linux-v6.1/drivers/gpu/drm/i915/display/
Dintel_dp_link_training.c135 * still taking into account any LTTPR common lane- rate/count limits. in intel_dp_init_lttpr()
317 int lane) in intel_dp_get_lane_adjust_tx_ffe_preset() argument
322 lane = min(lane, crtc_state->lane_count - 1); in intel_dp_get_lane_adjust_tx_ffe_preset()
323 tx_ffe = drm_dp_get_adjust_tx_ffe_preset(link_status, lane); in intel_dp_get_lane_adjust_tx_ffe_preset()
325 for (lane = 0; lane < crtc_state->lane_count; lane++) in intel_dp_get_lane_adjust_tx_ffe_preset()
326 tx_ffe = max(tx_ffe, drm_dp_get_adjust_tx_ffe_preset(link_status, lane)); in intel_dp_get_lane_adjust_tx_ffe_preset()
337 int lane) in intel_dp_get_lane_adjust_vswing_preemph() argument
345 lane = min(lane, crtc_state->lane_count - 1); in intel_dp_get_lane_adjust_vswing_preemph()
347 v = drm_dp_get_adjust_request_voltage(link_status, lane); in intel_dp_get_lane_adjust_vswing_preemph()
348 p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane); in intel_dp_get_lane_adjust_vswing_preemph()
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/Linux-v6.1/drivers/gpu/drm/amd/display/dc/core/
Ddc_link_dp.c344 uint8_t lane; in dp_fixed_vs_pe_read_lane_adjust() local
353 /* W/A to read lane settings requested by DPRX */ in dp_fixed_vs_pe_read_lane_adjust()
375 for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) { in dp_fixed_vs_pe_read_lane_adjust()
376 dpcd_lane_adjust[lane].bits.VOLTAGE_SWING_SET = (dprx_vs >> (2 * lane)) & 0x3; in dp_fixed_vs_pe_read_lane_adjust()
377 dpcd_lane_adjust[lane].bits.PRE_EMPHASIS_SET = (dprx_pe >> (2 * lane)) & 0x3; in dp_fixed_vs_pe_read_lane_adjust()
392 uint8_t lane = 0; in dp_fixed_vs_pe_set_retimer_lane_settings() local
399 for (lane = 0; lane < lane_count; lane++) { in dp_fixed_vs_pe_set_retimer_lane_settings()
401 dpcd_lane_adjust[lane].bits.VOLTAGE_SWING_SET << (2 * lane); in dp_fixed_vs_pe_set_retimer_lane_settings()
403 dpcd_lane_adjust[lane].bits.PRE_EMPHASIS_SET << (2 * lane); in dp_fixed_vs_pe_set_retimer_lane_settings()
479 DC_LOG_HW_LINK_TRAINING("%s\n %x rate = %x\n %x lane = %x framing = %x\n %x spread = %x\n", in dpcd_set_link_settings()
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/Linux-v6.1/drivers/media/platform/ti/omap3isp/
Domap3isp.h26 * @data_lane_shift: Data lane shifter
64 * struct isp_csiphy_lane: CCP2/CSI2 lane position and polarity
65 * @pos: position of the lane
66 * @pol: polarity of the lane
77 * struct isp_csiphy_lanes_cfg - CCP2/CSI2 lane configuration
79 * @clk: Clock lane configuration
99 * @lanecfg: CCP2/CSI2 lane configuration
114 * @lanecfg: CSI-2 lane configuration
/Linux-v6.1/include/linux/phy/
Dphy-mipi-dphy.h20 * Clock transitions and disable the Clock Lane HS-RX.
30 * send HS clock after the last associated Data Lane has
42 * the transmitter prior to any associated Data Lane beginning
53 * Lane LP-00 Line state immediately before the HS-0 Line
65 * should ignore any Clock Lane HS transitions, starting from
76 * Time, in picoseconds, for the Clock Lane receiver to enable
105 * Time, in picoseconds, for the Data Lane receiver to enable
137 * Lane LP-00 Line state immediately before the HS-0 Line
149 * shall ignore any Data Lane HS transitions, starting from
161 * should ignore any transitions on the Data Lane, following a
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/Linux-v6.1/drivers/net/ethernet/ti/
Dnetcp_xgbepcsr.c146 /* lane is 0 based */
148 void __iomem *serdes_regs, int lane) in netcp_xgbe_serdes_lane_config() argument
152 /* lane setup */ in netcp_xgbe_serdes_lane_config()
156 (0x200 * lane), in netcp_xgbe_serdes_lane_config()
162 reg_rmw(serdes_regs + (0x200 * lane) + 0x0380, in netcp_xgbe_serdes_lane_config()
166 reg_rmw(serdes_regs + (0x200 * lane) + 0x03c0, in netcp_xgbe_serdes_lane_config()
182 void __iomem *serdes_regs, int lane) in netcp_xgbe_serdes_lane_enable() argument
184 /* Set Lane Control Rate */ in netcp_xgbe_serdes_lane_enable()
185 writel(0xe0e9e038, serdes_regs + 0x1fe0 + (4 * lane)); in netcp_xgbe_serdes_lane_enable()
258 /* For 2 lane Phy-B, lane0 is actually lane1 */ in netcp_xgbe_serdes_write_tbus_addr()
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