Home
last modified time | relevance | path

Searched full:llcc (Results 1 – 24 of 24) sorted by relevance

/Linux-v6.1/include/linux/soc/qcom/
Dllcc-qcom.h49 * @slice_id: llcc slice id
50 * @slice_size: Size allocated for the llcc slice
58 * struct llcc_edac_reg_data - llcc edac registers data for each error type
82 /* LLCC TRP registers */
92 /* LLCC Common registers */
97 /* LLCC DRP registers */
110 * struct llcc_drv_data - Data associated with the llcc driver
111 * @regmap: regmap associated with the llcc device
112 * @bcast_regmap: regmap associated with llcc broadcast offset
114 * @edac_reg_offset: Offset of the LLCC EDAC registers
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/arm/msm/
Dqcom,llcc.yaml4 $id: http://devicetree.org/schemas/arm/msm/qcom,llcc.yaml#
14 LLCC (Last Level Cache Controller) provides last level of cache memory in SoC,
24 - qcom,sc7180-llcc
25 - qcom,sc7280-llcc
26 - qcom,sc8180x-llcc
27 - qcom,sc8280xp-llcc
28 - qcom,sdm845-llcc
29 - qcom,sm6350-llcc
30 - qcom,sm8150-llcc
31 - qcom,sm8250-llcc
[all …]
/Linux-v6.1/drivers/soc/qcom/
Dllcc-qcom.c20 #include <linux/soc/qcom/llcc-qcom.h>
59 * struct llcc_slice_config - Data associated with the llcc slice
61 * @slice_id: llcc slice id for each client
75 * When configured to 0 all ways in llcc are probed.
310 /* LLCC Common registers */
315 /* LLCC DRP registers */
337 /* LLCC Common registers */
342 /* LLCC DRP registers */
354 /* LLCC register offset starting from v1.0.0 */
360 /* LLCC register offset starting from v2.0.1 */
[all …]
DKconfig64 tristate "Qualcomm Technologies, Inc. LLCC driver"
68 Last Level Cache Controller(LLCC) driver for platforms such as,
69 SDM845. This provides interfaces to clients that use the LLCC.
70 Say yes here to enable LLCC slice driver.
DMakefile27 obj-$(CONFIG_QCOM_LLCC) += llcc-qcom.o
Dicc-bwmon.c680 .compatible = "qcom,sdm845-llcc-bwmon",
683 .compatible = "qcom,sc7280-llcc-bwmon",
/Linux-v6.1/drivers/edac/
Dqcom_edac.c12 #include <linux/soc/qcom/llcc-qcom.h>
265 "LLCC Data RAM correctable Error"); in dump_syn_reg()
269 "LLCC Data RAM uncorrectable Error"); in dump_syn_reg()
273 "LLCC Tag RAM correctable Error"); in dump_syn_reg()
277 "LLCC Tag RAM uncorrectable Error"); in dump_syn_reg()
348 edev_ctl = edac_device_alloc_ctl_info(0, "qcom-llcc", 1, "bank", in qcom_llcc_edac_probe()
359 edev_ctl->ctl_name = "llcc"; in qcom_llcc_edac_probe()
DKconfig515 As of now, it supports error reporting for Last Level Cache Controller (LLCC)
/Linux-v6.1/Documentation/devicetree/bindings/interconnect/
Dqcom,msm8998-bwmon.yaml20 (DDR) - called LLCC BWMON.
31 - const: qcom,sc7280-llcc-bwmon # BWMON v5
32 - const: qcom,sdm845-llcc-bwmon # BWMON v5
/Linux-v6.1/drivers/gpu/drm/msm/disp/dpu1/
Ddpu_core_perf.h20 * @DPU_CORE_PERF_DATA_BUS_ID_LLCC: MNOC/LLCC data bus
21 * @DPU_CORE_PERF_DATA_BUS_ID_EBI: LLCC/EBI data bus
Ddpu_crtc.h194 * @bw_split_vote : true if bw controlled by llcc/dram bw properties
Ddpu_hw_catalog.h776 * @min_llcc_ib minimum llcc ib vote in kbps
/Linux-v6.1/arch/arm64/boot/dts/qcom/
Dsdm850-samsung-w737.dts392 &llcc {
Dsm6350.dtsi1171 compatible = "qcom,sm6350-llcc";
Dsdm845.dtsi2133 llcc: system-cache-controller@1100000 { label
2134 compatible = "qcom,sdm845-llcc";
2141 compatible = "qcom,sdm845-llcc-bwmon";
Dsc8280xp.dtsi1249 compatible = "qcom,sc8280xp-llcc";
Dsm8250.dtsi331 idle-state-name = "cluster-llcc-off";
3055 compatible = "qcom,sm8250-llcc";
Dsc7280.dtsi3489 compatible = "qcom,sc7280-llcc-bwmon";
3579 compatible = "qcom,sc7280-llcc";
Dsm8350.dtsi2435 compatible = "qcom,sm8350-llcc";
Dsm8450.dtsi3088 compatible = "qcom,sm8450-llcc";
Dsc7180.dtsi2726 compatible = "qcom,sc7180-llcc";
Dsm8150.dtsi1764 compatible = "qcom,sm8150-llcc";
/Linux-v6.1/drivers/net/ethernet/sun/
Dcassini.h2200 { "LLCc?", 0xff00, 0x0300, OP_EQ, 2, S1_IPV4, 0, S1_CLNP, \
2298 { "LLCc?",0xff00, 0x0300, OP_EQ, 2, S1_IPV4, 0, S3_CLNP,
2378 { "LLCc?", 0xff00, 0x0300, OP_EQ, 2, S1_IPV4, 0, S1_CLNP,
2434 { "LLCc?", 0xff00, 0x0300, OP_EQ, 2, S1_IPV4, 0, S1_CLNP,
/Linux-v6.1/drivers/gpu/drm/msm/adreno/
Da6xx_gpu.c14 #include <linux/soc/qcom/llcc-qcom.h>