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/Linux-v6.6/drivers/media/pci/cx23885/
Daltera-ci.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * altera-ci.c
5 * CI driver in conjunction with NetUp Dual DVB-T/C RF CI card
13 * GPIO-0 ~INT in
14 * GPIO-1 TMS out
15 * GPIO-2 ~reset chips out
16 * GPIO-3 to GPIO-10 data/addr for CA in/out
17 * GPIO-11 ~CS out
18 * GPIO-12 AD_RG out
19 * GPIO-13 ~WR out
[all …]
/Linux-v6.6/Documentation/devicetree/bindings/powerpc/nintendo/
Dwii.txt11 - model : Should be "nintendo,wii"
12 - compatible : Should be "nintendo,wii"
16 This node represents the multi-function "Hollywood" chip, which packages
21 - compatible : Should be "nintendo,hollywood"
30 - compatible : should be "nintendo,hollywood-vi","nintendo,flipper-vi"
31 - reg : should contain the VI registers location and length
32 - interrupts : should contain the VI interrupt
41 - compatible : should be "nintendo,hollywood-pi","nintendo,flipper-pi"
42 - reg : should contain the PI registers location and length
46 Represents the "Flipper" interrupt controller within the "Hollywood" chip.
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/Linux-v6.6/Documentation/devicetree/bindings/timer/
Dsifive,clint.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Palmer Dabbelt <palmer@dabbelt.com>
11 - Anup Patel <anup.patel@wdc.com>
14 SiFive (and other RISC-V) SOCs include an implementation of the SiFive
15 Core Local Interruptor (CLINT) for M-mode timer and M-mode inter-processor
16 interrupts. It directly connects to the timer and inter-processor interrupt
17 lines of various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local
19 The clock frequency of CLINT is specified via "timebase-frequency" DT
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/Linux-v6.6/include/linux/usb/
Disp116x.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Board initialization code should put one of these into dev->platform_data
13 /* On-chip overcurrent detection */
25 /* Inter-io delay (ns). The chip is picky about access timings; it
Disp1362.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * board initialization code should put one of these into dev->platform_data
15 /* On-chip overcurrent protection */
25 /* chip can be resumed via H_WAKEUP pin */
37 /* Inter-io delay (ns). The chip is picky about access timings; it
/Linux-v6.6/drivers/mailbox/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
6 on-chip processors through queued messages and interrupt driven
16 Apple SoCs have various co-processors required for certain
70 running on the Cortex-M3 rWTM secure processor of the Armada 37xx
96 This driver provides support for inter-processor communication
184 module will be called mailbox-mpfs.
193 providing an interface for invoking the inter-process communication
206 tristate "APM SoC X-Gene SLIMpro Mailbox Controller"
209 An implementation of the APM X-Gene Interprocessor Communication
210 Mailbox (IPCM) between the ARM 64-bit cores and SLIMpro controller.
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/Linux-v6.6/Documentation/devicetree/bindings/usb/
Dusb.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Greg Kroah-Hartman <gregkh@linuxfoundation.org>
22 phy-names:
26 usb-phy:
27 $ref: /schemas/types.yaml#/definitions/phandle-array
36 UTMI+ PHY with an 8- or 16-bit interface if UTMI+ is selected, UTMI+ low
38 serial is specified and High-Speed Inter-Chip feature if HSIC is
44 maximum-speed:
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/Linux-v6.6/Documentation/translations/zh_CN/arch/loongarch/
Dirq-chip-model.rst1 .. SPDX-License-Identifier: GPL-2.0
3 .. include:: ../../disclaimer-zh_CN.rst
5 :Original: Documentation/arch/loongarch/irq-chip-model.rst
15 HTVECINTC（Hyper-Transport Vector Interrupt Controller）、PCH-PIC（LS7A芯片组的主中
16 断控制器）、PCH-LPC（LS7A芯片组的LPC中断控制器）和PCH-MSI（MSI中断控制器）。
19 全局中断控制器（每个芯片一个，所有核共享），而PCH-PIC/PCH-LPC/PCH-MSI是CPU外部的中
26 在这种模型里面，IPI（Inter-Processor Interrupt）和CPU本地时钟中断直接发送到CPUINTC，
27 CPU串口（UARTs）中断发送到LIOINTC，而其他所有设备的中断则分别发送到所连接的PCH-PIC/
28 PCH-LPC/PCH-MSI，然后被HTVECINTC统一收集，再发送到LIOINTC，最后到达CPUINTC::
30 +-----+ +---------+ +-------+
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/Linux-v6.6/Documentation/arch/loongarch/
Dirq-chip-model.rst1 .. SPDX-License-Identifier: GPL-2.0
4 IRQ chip model (hierarchy) of LoongArch
7 Currently, LoongArch based processors (e.g. Loongson-3A5000) can only work together
10 I/O Interrupt Controller), HTVECINTC (Hyper-Transport Vector Interrupt Controller),
11 PCH-PIC (Main Interrupt Controller in LS7A chipset), PCH-LPC (LPC Interrupt Controller
12 in LS7A chipset) and PCH-MSI (MSI Interrupt Controller).
14 CPUINTC is a per-core controller (in CPU), LIOINTC/EIOINTC/HTVECINTC are per-package
15 controllers (in CPU), while PCH-PIC/PCH-LPC/PCH-MSI are controllers out of CPU (i.e.,
22 In this model, IPI (Inter-Processor Interrupt) and CPU Local Timer interrupt go
24 interrupts go to PCH-PIC/PCH-LPC/PCH-MSI and gathered by HTVECINTC, and then go
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/Linux-v6.6/Documentation/userspace-api/media/
Dglossary.rst1 .. SPDX-License-Identifier: GPL-2.0 OR GFDL-1.1-no-invariants-or-later
51 **Field-programmable Gate Array**
56 See https://en.wikipedia.org/wiki/Field-programmable_gate_array.
65 together make a larger user-facing functional peripheral. For
73 **Inter-Integrated Circuit**
75 A multi-master, multi-slave, packet switched, single-ended,
77 like sub-device hardware components.
79 See http://www.nxp.com/docs/en/user-guide/UM10204.pdf.
87 Also known as chip.
113 - :term:`CEC API`;
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/Linux-v6.6/drivers/net/ethernet/apple/
Dbmac.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * mace.h - definitions for the registers in the "Big Mac"
17 #define XIFC 0x000 /* low-level interface control */
19 # define XIFLoopback 0x0002 /* Loopback-mode XIF enable */
20 # define MIILoopback 0x0004 /* Loopback-mode MII enable */
41 #define CHIPID 0x170 /* chip ID */
48 #define STATUS 0x200 /* status--reading this clears it */
53 # define RxAlignCntExp 0x00000004 /* Align-error counter expired */
54 # define RxCRCCntExp 0x00000008 /* CRC-error counter expired */
55 # define RxLenCntExp 0x00000010 /* Length-error counter expired */
[all …]
/Linux-v6.6/arch/arm/mach-shmobile/
Dpm-rcar-gen2.c1 // SPDX-License-Identifier: GPL-2.0
3 * R-Car Generation 2 Power management support
5 * Copyright (C) 2013 - 2015 Renesas Electronics Corporation
18 #include "rcar-gen2.h"
33 #define CA15RESCNT_CPUS 0xf /* CPU0-3 */
35 #define CA7RESCNT_CPUS 0xf /* CPU0-3 */
37 /* On-chip RAM */
38 #define ICRAM1 0xe63c0000 /* Inter Connect RAM1 (4 KiB) */
60 if (of_device_is_compatible(np, "arm,cortex-a15")) in rcar_gen2_pm_init()
62 else if (of_device_is_compatible(np, "arm,cortex-a7")) in rcar_gen2_pm_init()
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/Linux-v6.6/arch/powerpc/platforms/
DKconfig1 # SPDX-License-Identifier: GPL-2.0
37 bool "ePAPR para-virtualization support"
39 Enables ePAPR para-virtualization support for guests.
48 a hypervisor. This option is not user-selectable but should
65 bool "Device-tree based CPU feature discovery & setup"
101 chip, but it can potentially support other global timers
124 registers are used for inter-processor communication.
206 bool "On-chip CPU temperature sensor support"
209 G3 and G4 processors have an on-chip temperature sensor called the
210 'Thermal Assist Unit (TAU)', which, in theory, can measure the on-die
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/Linux-v6.6/Documentation/devicetree/bindings/display/
Dst,stih4xx.txt3 - sti-vtg: video timing generator
5 - compatible: "st,vtg"
6 - reg: Physical base address of the IP registers and length of memory mapped region.
8 - interrupts : VTG interrupt number to the CPU.
9 - st,slave: phandle on a slave vtg
11 - sti-vtac: video timing advanced inter dye communication Rx and TX
13 - compatible: "st,vtac-main" or "st,vtac-aux"
14 - reg: Physical base address of the IP registers and length of memory mapped region.
15 - clocks: from common clock binding: handle hardware IP needed clocks, the
17 See ../clocks/clock-bindings.txt for details.
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/Linux-v6.6/sound/soc/atmel/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 tristate "SoC Audio for the Atmel System-on-Chip"
31 in PDC mode configured using audio-graph-card in device-tree.
40 in DMA mode configured using audio-graph-card in device-tree.
43 tristate "SoC Audio support for WM8731-based At91sam9g20 evaluation board"
49 Say Y if you want to add support for SoC audio on WM8731-based
63 tristate "SoC Audio support for WM8731-based at91sam9x5 board"
91 tristate "ASoC driver for the Axentia TSE-850"
98 Axentia TSE-850 with a PCM5142 codec.
110 tristate "Support for Mikroe-PROTO board"
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/Linux-v6.6/drivers/net/ethernet/seeq/
Dsgiseeq.h1 /* SPDX-License-Identifier: GPL-2.0 */
77 #define SEEQ_TCMD_RB1 0x20 /* Register bank one w/multi-cast low byte */
78 #define SEEQ_TCMD_RB2 0x40 /* Register bank two w/multi-cast high byte */
98 #define SEEQ_HCTL_IPEND 0x00000002 /* IRQ is pending for the chip */
99 #define SEEQ_HCTL_IPG 0x00001000 /* Inter-packet gap */
100 #define SEEQ_HCTL_RFIX 0x00002000 /* At rxdc, clear end-of-packet */
/Linux-v6.6/drivers/mfd/
Dsi476x-cmd.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/mfd/si476x-cmd.c -- Subroutines implementing command
21 #include <linux/mfd/si476x-core.h>
177 if (core->revision != SI476X_REVISION_A10) { in si476x_core_parse_and_nag_about_error()
184 err = -EINVAL; in si476x_core_parse_and_nag_about_error()
188 err = -EINVAL; in si476x_core_parse_and_nag_about_error()
192 err = -EINVAL; in si476x_core_parse_and_nag_about_error()
196 err = -EINVAL; in si476x_core_parse_and_nag_about_error()
200 err = -EINVAL; in si476x_core_parse_and_nag_about_error()
203 cause = "Chip is busy"; in si476x_core_parse_and_nag_about_error()
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/Linux-v6.6/Documentation/ABI/testing/
Dsysfs-bus-usb10 This allows to avoid side-effects with drivers
28 drivers, non-authorized one are not. By default, wired
33 Contact: linux-usb@vger.kernel.org
67 What: /sys/bus/usb-serial/drivers/.../new_id
69 Contact: linux-usb@vger.kernel.org
72 extra bus folder "usb-serial" in sysfs; apart from that
97 If CONFIG_PM is set and a USB 2.0 lpm-capable device is plugged
113 If CONFIG_PM is set and a USB 3.0 lpm-capable device is plugged
141 attribute allows user-space to know whether the device is
145 an on-screen keyboard if the only wireless keyboard is
[all …]
/Linux-v6.6/drivers/irqchip/
Dirq-loongson-eiointc.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
81 /* EIO node 0 is in charge of inter-node interrupt dispatch */ in eiointc_set_irq_route()
96 struct eiointc_priv *priv = d->domain->host_data; in eiointc_set_irq_affinity()
101 cpumask_and(&intersect_affinity, &intersect_affinity, &priv->cpuspan_map); in eiointc_set_irq_affinity()
105 return -EINVAL; in eiointc_set_irq_affinity()
109 vector = d->hwirq; in eiointc_set_irq_affinity()
114 0x0, priv->node * CORES_PER_EIO_NODE); in eiointc_set_irq_affinity()
117 eiointc_set_irq_route(vector, cpu, priv->node, &priv->node_map); in eiointc_set_irq_affinity()
121 0x0, priv->node * CORES_PER_EIO_NODE); in eiointc_set_irq_affinity()
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/Linux-v6.6/drivers/net/wireless/broadcom/brcm80211/brcmfmac/
Dcommon.c1 // SPDX-License-Identifier: ISC
22 #include "chip.h"
68 MODULE_PARM_DESC(iapp, "Enable partial support for the obsoleted Inter-Access Point Protocol");
82 struct brcmf_pub *drvr = ifp->drvr; in brcmf_c_set_joinpref_default()
109 dload_buf->flag = cpu_to_le16(flag); in brcmf_c_download()
110 dload_buf->dload_type = cpu_to_le16(DL_TYPE_CLM); in brcmf_c_download()
111 dload_buf->len = cpu_to_le32(len); in brcmf_c_download()
112 dload_buf->crc = cpu_to_le32(0); in brcmf_c_download()
124 struct brcmf_pub *drvr = ifp->drvr; in brcmf_c_download_blob()
138 err = -ENOMEM; in brcmf_c_download_blob()
[all …]
/Linux-v6.6/sound/soc/tegra/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 tristate "SoC Audio for the Tegra System-on-Chip"
82 Config to enable the Inter-IC Sound (I2S) Controller which
83 implements full-duplex and bidirectional and single direction
84 point-to-point serial interfaces. It can interface with I2S
113 converts the multi-bit Pulse Code Modulation (PCM) audio input to
114 oversampled 1-bit Pulse Density Modulation (PDM) output. From the
116 that up-samples the input to the desired sampling rate by
118 the desired 1-bit output via Delta Sigma Modulation (DSM).
138 per-stream volume control or for master volume control.
[all …]
/Linux-v6.6/drivers/net/ethernet/microchip/
Denc28j60.c1 // SPDX-License-Identifier: GPL-2.0+
77 } debug = { -1 };
86 struct device *dev = &priv->spi->dev; in spi_read_buf()
87 u8 *rx_buf = priv->spi_transfer_buf + 4; in spi_read_buf()
88 u8 *tx_buf = priv->spi_transfer_buf; in spi_read_buf()
106 ret = spi_sync(priv->spi, &msg); in spi_read_buf()
123 struct device *dev = &priv->spi->dev; in spi_write_buf()
126 if (len > SPI_TRANSFER_BUF_LEN - 1 || len <= 0) in spi_write_buf()
127 ret = -EINVAL; in spi_write_buf()
129 priv->spi_transfer_buf[0] = ENC28J60_WRITE_BUF_MEM; in spi_write_buf()
[all …]
/Linux-v6.6/drivers/net/ethernet/amd/
Damd8111e.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
40 #define CHIPID 0x04 /* Chip ID register */
56 #define AUTOPOLL0 0x88 /* Auto-poll0 register */
57 #define AUTOPOLL1 0x8A /* Auto-poll1 register */
58 #define AUTOPOLL2 0x8C /* Auto-poll2 register */
59 #define AUTOPOLL3 0x8E /* Auto-poll3 register */
60 #define AUTOPOLL4 0x90 /* Auto-poll4 register */
61 #define AUTOPOLL5 0x92 /* Auto-poll5 register */
63 #define AP_VALUE 0x98 /* Auto-poll value register */
98 #define IFS1 0x18C /* Inter-frame spacing Part1 register */
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/Linux-v6.6/drivers/firmware/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
4 # see Documentation/kbuild/kconfig-language.rst.
19 provides a mechanism for inter-processor communication between SCP
71 bool "Add firmware-provided memory map to sysfs" if EXPERT
74 Add the firmware-provided (unmodified) memory map to /sys/firmware/memmap.
78 See also Documentation/ABI/testing/sysfs-firmware-memmap.
111 DMI-based module auto-loading.
223 warm-restart enter a special debug mode that allows the user to
239 bootloader or kernel can show basic video-output during boot for
240 user-guidance and debugging. Historically, x86 used the VESA BIOS
[all …]
/Linux-v6.6/drivers/net/ethernet/i825xx/
Dsun3_82586.h1 /* SPDX-License-Identifier: GPL-2.0-only */
8 * copyrights (c) 1994 by Michael Hipp (hippm@informatik.uni-tuebingen.de)
11 * crynwr-packet-driver by Russ Nelson
12 * Garret A. Wollman's i82586-driver for BSD
22 /* defines for the obio chip (not vme) */
53 char *iscp; /* pointer to the iscp-block */
65 char *scb_base; /* base-address of all 16-bit offsets */
79 unsigned short crc_errs; /* CRC-Error counter */
89 #define RUC_NOP 0x0000 /* NOP-command */
96 #define CUC_NOP 0x00 /* NOP-command */
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