| /Linux-v5.15/drivers/mailbox/ |
| D | stm32-ipcc.c | 53 spinlock_t lock; /* protect access to IPCC registers */
83 struct stm32_ipcc *ipcc = data; in stm32_ipcc_rx_irq() local
84 struct device *dev = ipcc->controller.dev; in stm32_ipcc_rx_irq()
90 proc_offset = ipcc->proc_id ? -IPCC_PROC_OFFST : IPCC_PROC_OFFST; in stm32_ipcc_rx_irq()
91 tosr = readl_relaxed(ipcc->reg_proc + proc_offset + IPCC_XTOYSR); in stm32_ipcc_rx_irq()
92 mr = readl_relaxed(ipcc->reg_proc + IPCC_XMR); in stm32_ipcc_rx_irq()
97 for (chan = 0; chan < ipcc->n_chans; chan++) { in stm32_ipcc_rx_irq()
103 mbox_chan_received_data(&ipcc->controller.chans[chan], NULL); in stm32_ipcc_rx_irq()
105 stm32_ipcc_set_bits(&ipcc->lock, ipcc->reg_proc + IPCC_XSCR, in stm32_ipcc_rx_irq()
116 struct stm32_ipcc *ipcc = data; in stm32_ipcc_tx_irq() local
[all …]
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| D | qcom-ipcc.c | 14 #include <dt-bindings/mailbox/qcom-ipcc.h>
18 /* IPCC Register offsets */
44 * @base: Base address of the IPCC frame associated to APSS
74 struct qcom_ipcc *ipcc = data; in qcom_ipcc_irq_fn() local
79 hwirq = readl(ipcc->base + IPCC_REG_RECV_ID); in qcom_ipcc_irq_fn()
83 virq = irq_find_mapping(ipcc->irq_domain, hwirq); in qcom_ipcc_irq_fn()
84 writel(hwirq, ipcc->base + IPCC_REG_RECV_SIGNAL_CLEAR); in qcom_ipcc_irq_fn()
93 struct qcom_ipcc *ipcc = irq_data_get_irq_chip_data(irqd); in qcom_ipcc_mask_irq() local
96 writel(hwirq, ipcc->base + IPCC_REG_RECV_SIGNAL_DISABLE); in qcom_ipcc_mask_irq()
101 struct qcom_ipcc *ipcc = irq_data_get_irq_chip_data(irqd); in qcom_ipcc_unmask_irq() local
[all …]
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| D | Kconfig | 222 tristate "STM32 IPCC Mailbox"
226 with hardware for Inter-Processor Communication Controller (IPCC)
267 tristate "Qualcomm Technologies, Inc. IPCC driver"
271 (IPCC) driver for MSM devices. The driver provides mailbox support for
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| D | Makefile | 50 obj-$(CONFIG_STM32_IPCC) += stm32-ipcc.o
60 obj-$(CONFIG_QCOM_IPCC) += qcom-ipcc.o
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| /Linux-v5.15/Documentation/devicetree/bindings/mailbox/ |
| D | qcom-ipcc.yaml | 4 $id: http://devicetree.org/schemas/mailbox/qcom-ipcc.yaml#
13 The Inter-Processor Communication Controller (IPCC) is a centralized hardware
20 protocol (protocol-id is 0). Refer include/dt-bindings/mailbox/qcom-ipcc.h
27 - qcom,sm6350-ipcc
28 - qcom,sm8250-ipcc
29 - qcom,sm8350-ipcc
30 - qcom,sc7280-ipcc
31 - const: qcom,ipcc
65 #include <dt-bindings/mailbox/qcom-ipcc.h>
68 compatible = "qcom,sm8250-ipcc", "qcom,ipcc";
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| D | st,stm32-ipcc.yaml | 4 $id: "http://devicetree.org/schemas/mailbox/st,stm32-ipcc.yaml#"
10 The IPCC block provides a non blocking signaling mechanism to post and
21 const: st,stm32mp1-ipcc
68 ipcc: mailbox@4c001000 {
69 compatible = "st,stm32mp1-ipcc";
77 clocks = <&rcc_clk IPCC>;
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| /Linux-v5.15/sound/soc/intel/catpt/ |
| D | ipc.c | 64 catpt_writel_shim(cdev, IPCC, header); in catpt_dsp_send_tx()
268 u32 isc, ipcc; in catpt_dsp_irq_handler() local
278 ipcc = catpt_readl_shim(cdev, IPCC); in catpt_dsp_irq_handler()
279 trace_catpt_ipc_reply(ipcc); in catpt_dsp_irq_handler()
280 catpt_dsp_copy_rx(cdev, ipcc); in catpt_dsp_irq_handler()
284 catpt_updatel_shim(cdev, IPCC, CATPT_IPCC_DONE, 0); in catpt_dsp_irq_handler()
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| D | dsp.c | 324 catpt_writel_shim(cdev, IPCC, CATPT_IPCC_DEFAULT); in catpt_dsp_set_regs_defaults()
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| /Linux-v5.15/arch/arm/boot/dts/ |
| D | stm32mp157a-microgea-stm32mp1.dtsi | 116 &ipcc {
128 mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>;
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| D | stm32mp157a-icore-stm32mp1.dtsi | 164 &ipcc {
176 mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>;
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| D | stm32mp15xx-osd32.dtsi | 211 &ipcc {
218 mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>;
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| D | stm32mp157c-odyssey-som.dtsi | 231 &ipcc {
243 mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>;
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| D | stm32mp157c-ed1.dts | 304 &ipcc {
316 mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>, <&ipcc 3>;
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| D | stm32mp15xx-dhcom-som.dtsi | 407 &ipcc {
419 mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>;
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| D | stm32mp15xx-dkx.dtsi | 447 &ipcc {
473 mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>, <&ipcc 3>;
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| D | stm32mp151.dtsi | 1092 ipcc: mailbox@4c001000 { label
1093 compatible = "st,stm32mp1-ipcc";
1102 clocks = <&rcc IPCC>;
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| /Linux-v5.15/arch/arm64/boot/dts/qcom/ |
| D | sm8350.dtsi | 10 #include <dt-bindings/mailbox/qcom-ipcc.h>
329 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
332 mboxes = <&ipcc IPCC_CLIENT_LPASS
353 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
356 mboxes = <&ipcc IPCC_CLIENT_CDSP
377 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
380 mboxes = <&ipcc IPCC_CLIENT_MPSS
412 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
415 mboxes = <&ipcc IPCC_CLIENT_SLPI
450 ipcc: mailbox@408000 { label
[all …]
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| D | sc7280.dtsi | 12 #include <dt-bindings/mailbox/qcom-ipcc.h>
304 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
307 mboxes = <&ipcc IPCC_CLIENT_LPASS
328 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
331 mboxes = <&ipcc IPCC_CLIENT_CDSP
352 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
355 mboxes = <&ipcc IPCC_CLIENT_MPSS
387 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS
390 mboxes = <&ipcc IPCC_CLIENT_WPSS
441 ipcc: mailbox@408000 { label
[all …]
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| D | sm8250.dtsi | 15 #include <dt-bindings/mailbox/qcom-ipcc.h>
399 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
402 mboxes = <&ipcc IPCC_CLIENT_LPASS
423 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
426 mboxes = <&ipcc IPCC_CLIENT_CDSP
447 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
450 mboxes = <&ipcc IPCC_CLIENT_SLPI
489 ipcc: mailbox@408000 { label
490 compatible = "qcom,sm8250-ipcc", "qcom,ipcc";
2104 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
[all …]
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| /Linux-v5.15/sound/soc/sof/intel/ |
| D | shim.h | 85 /* IPCX / IPCC */
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| /Linux-v5.15/include/dt-bindings/clock/ |
| D | stm32mp1-clks.h | 96 #define IPCC 83 macro
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| /Linux-v5.15/drivers/clk/ |
| D | clk-stm32mp1.c | 1934 PCLK(IPCC, "ipcc", "ck_mcu", 0, G_IPCC),
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| /Linux-v5.15/ |
| D | MAINTAINERS | 15569 QUALCOMM IPCC MAILBOX DRIVER
15573 F: Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml
15574 F: drivers/mailbox/qcom-ipcc.c
15575 F: include/dt-bindings/mailbox/qcom-ipcc.h
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