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/Linux-v6.1/Documentation/devicetree/bindings/mmc/
Dmtk-sd.yaml118 parent of source clock, used for HS400 mode to get 400Mhz source clock.
121 hs400-ds-delay:
124 HS400 DS delay setting.
137 mediatek,hs400-cmd-int-delay:
140 HS400 command internal delay setting.
146 mediatek,hs400-cmd-resp-sel-rising:
149 HS400 command response sample selection.
150 If present, HS400 command responses are sampled on rising edges.
151 If not present, HS400 command responses are sampled on falling edges.
153 mediatek,hs400-ds-dly3:
[all …]
Dnvidia,tegra20-sdhci.yaml101 The DQS trim values are only used on controllers which support HS400
102 timing. Only SDMMC4 on Tegra210 and Tegra186 supports HS400.
110 description: Specify DQS trim value for HS400 timing.
137 nvidia,pad-autocal-pull-down-offset-hs400:
138 description: Specify drive strength calibration offsets for HS400 mode.
159 and HS400 timing specific values are used in corresponding modes if
172 nvidia,pad-autocal-pull-up-offset-hs400:
173 description: Specify drive strength calibration offsets for HS400 mode.
Dsamsung,exynos-dw-mshc.yaml63 See also samsung,dw-mshc-hs400-timing property.
65 samsung,dw-mshc-hs400-timing:
75 The value of CIU TX and RX clock phase shift value for HS400 mode
97 See also samsung,dw-mshc-hs400-timing property.
102 RCLK (Data strobe) delay to control HS400 mode (Latency value for delay
Dmmc-controller.yaml215 mmc-hs400-1_2v:
218 eMMC HS400 mode (1.2V I/O) is supported.
220 mmc-hs400-1_8v:
223 eMMC HS400 mode (1.8V I/O) is supported.
225 mmc-hs400-enhanced-strobe:
228 eMMC HS400 enhanced strobe mode is supported
230 no-mmc-hs400:
233 All eMMC HS400 modes are not supported.
Dcdns,sdhci.yaml93 HS200, HS400 and HS400_ES.
100 Value of the delay introduced on the sdclk output for HS200, HS400 and
109 HS400 / HS400_ES speed modes.
132 mmc-hs400-1_8v;
Dsdhci-sprd.txt40 - sprd,phy-delay-mmc-hs400: Delay value for MMC HS400 timing.
41 - sprd,phy-delay-mmc-hs400es: Delay value for MMC HS400 enhanced strobe timing.
Dsdhci-am654.yaml122 ti,otap-del-sel-hs400:
123 description: Output tap delay for eMMC HS400 timing
185 description: strobe select delay for HS400 speed mode.
231 ti,otap-del-sel-hs400 = <0x0>;
Dbrcm,sdhci-brcmstb.yaml110 mmc-hs400-1_8v;
111 mmc-hs400-enhanced-strobe;
/Linux-v6.1/drivers/mmc/host/
Dsdhci-acpi.c494 * while HS400 tuning is in progress we end up with mismatched driver in amd_select_drive_strength()
495 * strengths between the controller and the card. HS400 tuning requires in amd_select_drive_strength()
496 * switching from HS400->DDR52->HS->HS200->HS400. So the driver mismatch in amd_select_drive_strength()
504 * card's timing to HS200 or HS400. The card will use the default driver in amd_select_drive_strength()
525 * The initialization sequence for HS400 is:
526 * HS->HS200->Perform Tuning->HS->HS400
529 * HS400->DDR52->HS->HS200->Perform Tuning->HS->HS400
531 * The AMD eMMC Controller can only use the tuned clock while in HS200 and HS400
534 * HS400, we can re-enable the tuned clock.
559 /* DLL is only required for HS400 */ in amd_set_ios()
[all …]
Drenesas_sdhi.h17 u32 tap; /* sampling clock position for SDR104/HS400 (8 TAP) */
18 u32 tap_hs400_4tap; /* sampling clock position for HS400 (4 TAP) */
Dsdhci-xenon-phy.c318 * and before HS400 data strobe setting.
436 /* Set HS400 Data Strobe and Enhanced Strobe */
449 dev_dbg(mmc_dev(host->mmc), "starts HS400 strobe delay adjustment\n"); in xenon_emmc_phy_strobe_delay_adj()
459 * 1. card is in HS400 mode and in xenon_emmc_phy_strobe_delay_adj()
638 /* Hardware team recommend a value for HS400 */ in xenon_emmc_phy_set()
736 * HS400 set Data Strobe and Enhanced Strobe if it is supported.
Ddw_mmc-exynos.c253 * related to HS400 in dw_mci_exynos_config_hs400()
259 "cannot configure HS400, unsupported chipset\n"); in dw_mci_exynos_config_hs400()
346 /* Configure setting for HS400 */ in dw_mci_exynos_set_ios()
395 "samsung,dw-mshc-hs400-timing", timing, 2); in dw_mci_exynos_parse_dt()
Dsdhci-xenon.c193 * Xenon defines different values for HS200 and HS400
284 * HS400/HS200/eMMC HS doesn't have Preset Value register. in xenon_set_ios()
285 * However, sdhci_set_ios will read HS400/HS200 Preset register. in xenon_set_ios()
286 * Disable Preset Value register for HS400/HS200. in xenon_set_ios()
Dsdhci-of-esdhc.c682 /* Limit clock division for HS400 200MHz clock for quirk. */ in esdhc_of_set_clock()
738 /* Additional setting for HS400. */ in esdhc_of_set_clock()
1125 /* Recover HS400 tuning flag */ in esdhc_execute_tuning()
1142 /* Recover HS400 tuning flag */ in esdhc_execute_tuning()
1175 * There are specific registers setting for HS400 mode. in esdhc_set_uhs_signaling()
1176 * Clean all of them if controller is in HS400 mode to in esdhc_set_uhs_signaling()
1177 * exit HS400 mode before re-setting any speed mode. in esdhc_set_uhs_signaling()
Dsdhci-msm.c482 * HS400/HS200 timing mode).
832 * Select HS400 mode using the HC_SELECT_IN from VENDOR SPEC in msm_hc_select_hs400()
871 * eMMC specific HS200/HS400 doesn't have their respective modes
875 * HS400 - This involves multiple configurations
877 * Then when switching to DDR @ 400MHz (HS400) we use
883 * HS400 - divided clock (free running MCLK/2)
909 * Retuning in HS400 (DDR mode) will fail, just reset the in sdhci_msm_cdclp533_calibration()
1089 * Retuning in HS400 (DDR mode) will fail, just reset the in sdhci_msm_hs400_dll_calibration()
1124 * Tuning is required for SDR104, HS200 and HS400 cards and in sdhci_msm_is_tuning_needed()
1203 * HS400 settings. in sdhci_msm_execute_tuning()
[all …]
/Linux-v6.1/arch/arm64/boot/dts/exynos/
Dexynos7885-jackpotlte.dts66 mmc-hs400-1_8v;
69 mmc-hs400-enhanced-strobe;
76 samsung,dw-mshc-hs400-timing = <0 2>;
Dexynos850-e850-96.dts140 mmc-hs400-1_8v;
143 mmc-hs400-enhanced-strobe;
150 samsung,dw-mshc-hs400-timing = <0 2>;
/Linux-v6.1/include/linux/mmc/
Dhost.h181 /* Prepare HS400 target operating frequency depending host driver */
184 /* Execute HS400 tuning depending host driver */
187 /* Prepare switch to DDR during the HS400 init sequence */
190 /* Prepare for switching from HS400 to HS200 */
193 /* Complete selection of HS400 */
402 #define MMC_CAP2_HS400_1_8V (1 << 15) /* Can support HS400 1.8V */
403 #define MMC_CAP2_HS400_1_2V (1 << 16) /* Can support HS400 1.2V */
/Linux-v6.1/arch/arm64/boot/dts/rockchip/
Drk3399-nanopc-t4.dts113 mmc-hs400-1_8v;
114 mmc-hs400-enhanced-strobe;
/Linux-v6.1/drivers/mmc/core/
Dhost.c262 mmc_of_parse_timing_phase(dev, "clk-phase-mmc-hs400", in mmc_of_parse_clk_phase()
398 if (device_property_read_bool(dev, "mmc-hs400-1_8v")) in mmc_of_parse()
400 if (device_property_read_bool(dev, "mmc-hs400-1_2v")) in mmc_of_parse()
402 if (device_property_read_bool(dev, "mmc-hs400-enhanced-strobe")) in mmc_of_parse()
410 if (device_property_read_bool(dev, "no-mmc-hs400")) in mmc_of_parse()
603 dev_warn(dev, "drop HS400 support since no 8-bit bus\n"); in mmc_validate_host_caps()
/Linux-v6.1/arch/arm64/boot/dts/sprd/
Dwhale2.dtsi148 sprd,phy-delay-mmc-hs400 = <0x44 0x7f 0x2e 0x2e>;
158 mmc-hs400-enhanced-strobe;
159 mmc-hs400-1_8v;
/Linux-v6.1/arch/arm64/boot/dts/renesas/
Dr8a774e1-hihope-rzg2h.dts40 mmc-hs400-1_8v;
Dr8a774b1-hihope-rzg2n-rev2.dts40 mmc-hs400-1_8v;
Dr8a774b1-hihope-rzg2n.dts40 mmc-hs400-1_8v;
/Linux-v6.1/arch/arm64/boot/dts/qcom/
Dmsm8994-huawei-angler-rev-101.dts45 mmc-hs400-1_8v;

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