Home
last modified time | relevance | path

Searched full:hs400 (Results 1 – 25 of 94) sorted by relevance

1234

/Linux-v5.15/Documentation/devicetree/bindings/mmc/
Dmtk-sd.yaml87 parent of source clock, used for HS400 mode to get 400Mhz source clock.
90 hs400-ds-delay:
93 HS400 DS delay setting.
106 mediatek,hs400-cmd-int-delay:
109 HS400 command internal delay setting.
115 mediatek,hs400-cmd-resp-sel-rising:
118 HS400 command response sample selection.
119 If present, HS400 command responses are sampled on rising edges.
120 If not present, HS400 command responses are sampled on falling edges.
171 hs400-ds-delay = <0x14015>;
[all …]
Dnvidia,tegra20-sdhci.txt79 - nvidia,pad-autocal-pull-up-offset-hs400,
80 nvidia,pad-autocal-pull-down-offset-hs400 : Specify drive strength
81 calibration offsets for HS400 mode.
86 - nvidia,dqs-trim : Specify DQS trim value for HS400 timing
94 - The SDR104 and HS400 timing specific values are used in
104 HS400 timing. Only SDMMC4 on Tegra210 and Tegra 186 supports
105 HS400.
Dmmc-controller.yaml208 mmc-hs400-1_2v:
211 eMMC HS400 mode (1.2V I/O) is supported.
213 mmc-hs400-1_8v:
216 eMMC HS400 mode (1.8V I/O) is supported.
218 mmc-hs400-enhanced-strobe:
221 eMMC HS400 enhanced strobe mode is supported
223 no-mmc-hs400:
226 All eMMC HS400 modes are not supported.
Dexynos-dw-mshc.txt39 * samsung,dw-mshc-hs400-timing: Specifies the value of CIU TX and RX clock phase
40 shift value for hs400 mode operation.
55 * samsung,read-strobe-delay: RCLK (Data strobe) delay to control HS400 mode
89 samsung,dw-mshc-hs400-timing = <0 2>;
Dcdns,sdhci.yaml93 HS200, HS400 and HS400_ES.
100 Value of the delay introduced on the sdclk output for HS200, HS400 and
109 HS400 / HS400_ES speed modes.
132 mmc-hs400-1_8v;
Dsdhci-sprd.txt40 - sprd,phy-delay-mmc-hs400: Delay value for MMC HS400 timing.
41 - sprd,phy-delay-mmc-hs400es: Delay value for MMC HS400 enhanced strobe timing.
Dsdhci-am654.yaml116 ti,otap-del-sel-hs400:
117 description: Output tap delay for eMMC HS400 timing
179 description: strobe select delay for HS400 speed mode.
218 ti,otap-del-sel-hs400 = <0x0>;
Dbrcm,sdhci-brcmstb.txt39 mmc-hs400-1_8v;
40 mmc-hs400-enhanced-strobe;
/Linux-v5.15/drivers/mmc/host/
Dsdhci-acpi.c570 * while HS400 tuning is in progress we end up with mismatched driver in amd_select_drive_strength()
571 * strengths between the controller and the card. HS400 tuning requires in amd_select_drive_strength()
572 * switching from HS400->DDR52->HS->HS200->HS400. So the driver mismatch in amd_select_drive_strength()
580 * card's timing to HS200 or HS400. The card will use the default driver in amd_select_drive_strength()
601 * The initialization sequence for HS400 is:
602 * HS->HS200->Perform Tuning->HS->HS400
605 * HS400->DDR52->HS->HS200->Perform Tuning->HS->HS400
607 * The AMD eMMC Controller can only use the tuned clock while in HS200 and HS400
610 * HS400, we can re-enable the tuned clock.
635 /* DLL is only required for HS400 */ in amd_set_ios()
[all …]
Drenesas_sdhi.h17 u32 tap; /* sampling clock position for SDR104/HS400 (8 TAP) */
18 u32 tap_hs400_4tap; /* sampling clock position for HS400 (4 TAP) */
Dsdhci-xenon-phy.c318 * and before HS400 data strobe setting.
436 /* Set HS400 Data Strobe and Enhanced Strobe */
449 dev_dbg(mmc_dev(host->mmc), "starts HS400 strobe delay adjustment\n"); in xenon_emmc_phy_strobe_delay_adj()
459 * 1. card is in HS400 mode and in xenon_emmc_phy_strobe_delay_adj()
638 /* Hardware team recommend a value for HS400 */ in xenon_emmc_phy_set()
736 * HS400 set Data Strobe and Enhanced Strobe if it is supported.
Ddw_mmc-exynos.c239 * related to HS400 in dw_mci_exynos_config_hs400()
244 "cannot configure HS400, unsupported chipset\n"); in dw_mci_exynos_config_hs400()
331 /* Configure setting for HS400 */ in dw_mci_exynos_set_ios()
380 "samsung,dw-mshc-hs400-timing", timing, 2); in dw_mci_exynos_parse_dt()
Dsdhci-xenon.c193 * Xenon defines different values for HS200 and HS400
294 * HS400/HS200/eMMC HS doesn't have Preset Value register. in xenon_set_ios()
295 * However, sdhci_set_ios will read HS400/HS200 Preset register. in xenon_set_ios()
296 * Disable Preset Value register for HS400/HS200. in xenon_set_ios()
Drenesas_sdhi_core.c367 /* Set HS400 mode */ in renesas_sdhi_hs400_complete()
374 /* Gen3 can't do automatic tap correction with HS400, so disable it */ in renesas_sdhi_hs400_complete()
385 /* Set the sampling clock selection range of HS400 mode */ in renesas_sdhi_hs400_complete()
515 /* Reset HS400 mode */ in renesas_sdhi_reset_hs400_mode()
714 * With HS400, the DAT signal is based on DS, not CLK. in renesas_sdhi_manual_correction()
778 * Skip checking SCC errors when running on 4 taps in HS400 mode as in renesas_sdhi_check_scc_error()
/Linux-v5.15/arch/arm64/boot/dts/rockchip/
Drk3399-nanopc-t4.dts113 mmc-hs400-1_8v;
114 mmc-hs400-enhanced-strobe;
/Linux-v5.15/drivers/clk/renesas/
Drcar-cpg-lib.c99 * 0 0 (1) 1 (4) 4 : SDR104 / HS200 / HS400 (8 TAP)
105 * 0 1 (2) 0 (2) 4 : SDR104 / HS200 / HS400 (4 TAP)
111 * table when searching for suitable settings. This is because HS400 on
/Linux-v5.15/arch/arm64/boot/dts/sprd/
Dwhale2.dtsi146 sprd,phy-delay-mmc-hs400 = <0x44 0x7f 0x2e 0x2e>;
156 mmc-hs400-enhanced-strobe;
157 mmc-hs400-1_8v;
/Linux-v5.15/include/linux/mmc/
Dhost.h162 /* Prepare HS400 target operating frequency depending host driver */
165 /* Prepare switch to DDR during the HS400 init sequence */
168 /* Prepare for switching from HS400 to HS200 */
171 /* Complete selection of HS400 */
380 #define MMC_CAP2_HS400_1_8V (1 << 15) /* Can support HS400 1.8V */
381 #define MMC_CAP2_HS400_1_2V (1 << 16) /* Can support HS400 1.2V */
/Linux-v5.15/drivers/mmc/core/
Dhost.c253 mmc_of_parse_timing_phase(dev, "clk-phase-mmc-hs400", in mmc_of_parse_clk_phase()
389 if (device_property_read_bool(dev, "mmc-hs400-1_8v")) in mmc_of_parse()
391 if (device_property_read_bool(dev, "mmc-hs400-1_2v")) in mmc_of_parse()
393 if (device_property_read_bool(dev, "mmc-hs400-enhanced-strobe")) in mmc_of_parse()
401 if (device_property_read_bool(dev, "no-mmc-hs400")) in mmc_of_parse()
Ddebugfs.c152 "mmc HS400 enhanced strobe" : "mmc HS400"; in mmc_ios_show()
Dmmc.c1163 * HS400 mode requires 8-bit bus width in mmc_select_hs400()
1205 pr_err("%s: switch to bus width for hs400 failed, err:%d\n", in mmc_select_hs400()
1210 /* Switch card to HS400 */ in mmc_select_hs400()
1218 pr_err("%s: switch to hs400 failed, err:%d\n", in mmc_select_hs400()
1223 /* Set host controller to HS400 timing and frequency */ in mmc_select_hs400()
1258 /* Switch HS400 to HS DDR */ in mmc_hs400_to_hs200()
1310 /* Prepare tuning for HS400 mode. */ in mmc_hs400_to_hs200()
1405 /* Switch card to HS400 */ in mmc_select_hs400es()
1418 /* Set host controller to HS400 timing and frequency */ in mmc_select_hs400es()
1539 * conditions for HS200 and HS400, which sends CMD21 to the device.
[all …]
/Linux-v5.15/arch/arm64/boot/dts/renesas/
Dr8a774e1-hihope-rzg2h.dts40 mmc-hs400-1_8v;
Dr8a774b1-hihope-rzg2n-rev2.dts40 mmc-hs400-1_8v;
Dr8a774b1-hihope-rzg2n.dts40 mmc-hs400-1_8v;
/Linux-v5.15/arch/arm64/boot/dts/mediatek/
Dmt8183-pumpkin.dts134 mmc-hs400-1_8v;
138 hs400-ds-delay = <0x12814>;

1234