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/Linux-v6.6/drivers/mmc/host/
Dsdhci-acpi.c480 * read from the HS200 (SDR104) preset register. in amd_select_drive_strength()
496 * switching from HS400->DDR52->HS->HS200->HS400. So the driver mismatch in amd_select_drive_strength()
504 * card's timing to HS200 or HS400. The card will use the default driver in amd_select_drive_strength()
526 * HS->HS200->Perform Tuning->HS->HS400
529 * HS400->DDR52->HS->HS200->Perform Tuning->HS->HS400
531 * The AMD eMMC Controller can only use the tuned clock while in HS200 and HS400
533 * If we have previously performed tuning and switch back to HS200 or
629 * b) The HS200 and HS400 driver strengths don't match. in sdhci_acpi_emmc_amd_probe_slot()
632 * strength of B. As part of initializing HS400, HS200 tuning in sdhci_acpi_emmc_amd_probe_slot()
638 * SDR25 => 25 MHz, SDR50 => 50 MHz. Additionally the HS200 and in sdhci_acpi_emmc_amd_probe_slot()
[all …]
Dsdhci-xenon.c193 * Xenon defines different values for HS200 and HS400
284 * HS400/HS200/eMMC HS doesn't have Preset Value register. in xenon_set_ios()
285 * However, sdhci_set_ios will read HS400/HS200 Preset register. in xenon_set_ios()
286 * Disable Preset Value register for HS400/HS200. in xenon_set_ios()
426 /* Disable HS200 on Armada AP806 */ in xenon_probe_params()
/Linux-v6.6/Documentation/devicetree/bindings/mmc/
Dcdns,sdhci.yaml95 HS200, HS400 and HS400_ES.
102 Value of the delay introduced on the sdclk output for HS200, HS400 and
153 mmc-hs200-1_8v;
Dsdhci-sprd.txt39 - sprd,phy-delay-mmc-hs200: Delay value for MMC HS200 timing.
Dmmc-controller.yaml205 mmc-hs200-1_2v:
208 eMMC HS200 mode (1.2V I/O) is supported.
210 mmc-hs200-1_8v:
213 eMMC HS200 mode (1.8V I/O) is supported.
Dsdhci-am654.yaml115 ti,otap-del-sel-hs200:
116 description: Output tap delay for eMMC HS200 timing
235 ti,otap-del-sel-hs200 = <0x5>;
Dmtk-sd.yaml101 mediatek,hs200-cmd-int-delay:
104 HS200 command internal delay setting.
327 mediatek,hs200-cmd-int-delay = <26>;
Dhi3798cv200-dw-mshc.txt37 mmc-hs200-1_8v;
Damlogic,meson-mx-sdhc.yaml18 It supports eMMC spec 4.4x/4.5x including HS200 (up to 100MHz clock).
Dbrcm,sdhci-brcmstb.yaml109 mmc-hs200-1_8v;
/Linux-v6.6/arch/arm64/boot/dts/mediatek/
Dmt7986a-bananapi-bpi-r3-emmc.dtso19 mmc-hs200-1_8v;
/Linux-v6.6/arch/arm/boot/dts/rockchip/
Drk3288-tinker-s.dts22 mmc-hs200-1_8v;
/Linux-v6.6/arch/arm64/boot/dts/rockchip/
Drk3328-nanopi-r2c-plus.dts26 mmc-hs200-1_8v;
Drk3368-orion-r68-meta.dts170 mmc-hs200-1_2v;
171 mmc-hs200-1_8v;
/Linux-v6.6/arch/arm64/boot/dts/qcom/
Dipq5018-rdp432-c2.dts35 mmc-hs200-1_8v;
Dipq5332-rdp441.dts28 mmc-hs200-1_8v;
Dipq5332-rdp474.dts28 mmc-hs200-1_8v;
Dipq5332-rdp468.dts35 mmc-hs200-1_8v;
Dipq5332-rdp442.dts42 mmc-hs200-1_8v;
/Linux-v6.6/arch/riscv/boot/dts/microchip/
Dmpfs-polarberry.dts74 mmc-hs200-1_8v;
/Linux-v6.6/arch/arm64/boot/dts/sprd/
Dwhale2.dtsi149 sprd,phy-delay-mmc-hs200 = <0x0 0x8c 0x8c 0x8c>;
160 mmc-hs200-1_8v;
/Linux-v6.6/arch/arm64/boot/dts/freescale/
Dfsl-ls1012a-rdb.dts37 mmc-hs200-1_8v;
/Linux-v6.6/arch/arm/boot/dts/broadcom/
Dbcm2711-rpi-cm4.dtsi53 mmc-hs200-1_8v;
/Linux-v6.6/drivers/mmc/core/
Dmmc.c1183 pr_err("%s: switch to high-speed from hs200 failed, err:%d\n", in mmc_select_hs400()
1303 /* Switch HS to HS200 */ in mmc_hs400_to_hs200()
1315 * For HS200, CRC errors are not a reliable way to know the switch in mmc_hs400_to_hs200()
1453 * For device supporting HS200 mode, the following sequence
1456 * 2. switch to HS200 mode
1481 * switch to HS200 mode if bus width is set successfully. in mmc_select_hs200()
1497 * NB: We can't move to full (HS200) speeds until after we've in mmc_select_hs200()
1506 * For HS200, CRC errors are not a reliable way to know the in mmc_select_hs200()
1534 * Activate High Speed, HS200 or HS400ES mode if supported.
1574 * conditions for HS200 and HS400, which sends CMD21 to the device.
/Linux-v6.6/arch/arm64/boot/dts/exynos/
Dexynos7885-jackpotlte.dts66 mmc-hs200-1_8v;

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