Searched full:harts (Results 1 – 15 of 15) sorted by relevance
| /Linux-v6.1/arch/riscv/kernel/ |
| D | sbi.c | 123 * sbi_shutdown() - Remove all the harts from executing supervisor code.
413 * @cpu_mask: A cpu mask containing all the target harts.
424 * sbi_remote_fence_i() - Execute FENCE.I instruction on given remote harts.
425 * @cpu_mask: A cpu mask containing all the target harts.
438 * harts for the specified virtual address range.
439 * @cpu_mask: A cpu mask containing all the target harts.
456 * remote harts for a virtual address range belonging to a specific ASID.
458 * @cpu_mask: A cpu mask containing all the target harts.
477 * harts for the specified guest physical address range.
478 * @cpu_mask: A cpu mask containing all the target harts.
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| D | traps.c | 226 * harts concurrently. This isn't a real spinlock because the lock side must
240 * overflow stack. Tell any other concurrent overflowing harts that in handle_bad_stack()
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| D | machine_kexec.c | 128 * harts and possibly devices etc) for a kexec reboot.
202 * executed. We assume at this point that all other harts are
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| D | head.S | 190 /* We lack SMP support or have too many harts, so park this hart */
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| D | entry.S | 409 * harts are concurrently overflowing their kernel stacks. We could
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| /Linux-v6.1/arch/riscv/mm/ |
| D | cacheflush.c | 32 * informs the remote harts they need to flush their local instruction caches.
35 * IPIs for harts that are not currently executing a MM context and instead
55 * Flush the I$ of other harts concurrently executing, and mark them as in flush_icache_mm()
119 pr_warn("cbom-block-size mismatched between harts %lu and %lu\n", in riscv_init_cbom_blocksize()
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| D | context.c | 276 * shoot downs, so instead we send an IPI that informs the remote harts they
279 * machine, ie 'make -j') we avoid the IPIs for harts that are not currently
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| /Linux-v6.1/arch/csky/abiv2/ |
| D | cacheflush.c | 77 * Flush the I$ of other harts concurrently executing, and mark them as in flush_icache_mm_range()
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| /Linux-v6.1/Documentation/devicetree/bindings/timer/ |
| D | sifive,clint.yaml | 17 lines of various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local
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| /Linux-v6.1/Documentation/devicetree/bindings/interrupt-controller/ |
| D | riscv,cpu-intc.txt | 23 a PLIC interrupt property will typically list the HLICs for all present HARTs
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| D | sifive,plic-1.0.0.yaml | 18 in an 4 core system with 2-way SMT, you have 8 harts and probably at least two
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| /Linux-v6.1/drivers/clocksource/ |
| D | timer-riscv.c | 60 * It is guaranteed that all the timers across all the harts are synchronized
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| /Linux-v6.1/Documentation/devicetree/bindings/riscv/ |
| D | cpus.yaml | 24 having four harts.
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| /Linux-v6.1/drivers/perf/ |
| D | riscv_pmu_sbi.c | 46 * RISC-V doesn't have hetergenous harts yet. This need to be part of
47 * per_cpu in case of harts with different pmu counters
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| /Linux-v6.1/Documentation/devicetree/bindings/cpu/ |
| D | idle-states.yaml | 55 On RISC-V systems, the HARTs (or CPUs) [6] can be put in platform specific
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