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/Linux-v6.6/drivers/net/ethernet/stmicro/stmmac/
Ddwmac-ipq806x.c2 * Qualcomm Atheros IPQ806x GMAC glue layer
115 static int get_clk_div_sgmii(struct ipq806x_gmac *gmac, unsigned int speed) in get_clk_div_sgmii() argument
117 struct device *dev = &gmac->pdev->dev; in get_clk_div_sgmii()
141 static int get_clk_div_rgmii(struct ipq806x_gmac *gmac, unsigned int speed) in get_clk_div_rgmii() argument
143 struct device *dev = &gmac->pdev->dev; in get_clk_div_rgmii()
167 static int ipq806x_gmac_set_speed(struct ipq806x_gmac *gmac, unsigned int speed) in ipq806x_gmac_set_speed() argument
172 switch (gmac->phy_mode) { in ipq806x_gmac_set_speed()
174 div = get_clk_div_rgmii(gmac, speed); in ipq806x_gmac_set_speed()
175 clk_bits = NSS_COMMON_CLK_GATE_RGMII_RX_EN(gmac->id) | in ipq806x_gmac_set_speed()
176 NSS_COMMON_CLK_GATE_RGMII_TX_EN(gmac->id); in ipq806x_gmac_set_speed()
[all …]
Ddwmac-sunxi.c32 struct sunxi_priv_data *gmac = priv; in sun7i_gmac_init() local
35 if (gmac->regulator) { in sun7i_gmac_init()
36 ret = regulator_enable(gmac->regulator); in sun7i_gmac_init()
41 /* Set GMAC interface port mode in sun7i_gmac_init()
43 * The GMAC TX clock lines are configured by setting the clock in sun7i_gmac_init()
47 if (phy_interface_mode_is_rgmii(gmac->interface)) { in sun7i_gmac_init()
48 clk_set_rate(gmac->tx_clk, SUN7I_GMAC_GMII_RGMII_RATE); in sun7i_gmac_init()
49 clk_prepare_enable(gmac->tx_clk); in sun7i_gmac_init()
50 gmac->clk_enabled = 1; in sun7i_gmac_init()
52 clk_set_rate(gmac->tx_clk, SUN7I_GMAC_MII_RATE); in sun7i_gmac_init()
[all …]
Ddwmac-anarion.c27 static uint32_t gmac_read_reg(struct anarion_gmac *gmac, uint8_t reg) in gmac_read_reg() argument
29 return readl(gmac->ctl_block + reg); in gmac_read_reg()
32 static void gmac_write_reg(struct anarion_gmac *gmac, uint8_t reg, uint32_t val) in gmac_write_reg() argument
34 writel(val, gmac->ctl_block + reg); in gmac_write_reg()
40 struct anarion_gmac *gmac = priv; in anarion_gmac_init() local
43 gmac_write_reg(gmac, GMAC_RESET_CONTROL_REG, 1); in anarion_gmac_init()
45 sw_config = gmac_read_reg(gmac, GMAC_SW_CONFIG_REG); in anarion_gmac_init()
47 sw_config |= (gmac->phy_intf_sel & GMAC_CONFIG_INTF_SEL_MASK); in anarion_gmac_init()
48 gmac_write_reg(gmac, GMAC_SW_CONFIG_REG, sw_config); in anarion_gmac_init()
50 gmac_write_reg(gmac, GMAC_RESET_CONTROL_REG, 0); in anarion_gmac_init()
[all …]
Ddwmac-sun8i.c38 * @syscon_field reg_field for the syscon's gmac register
589 struct sunxi_priv_data *gmac = priv; in sun8i_dwmac_init() local
592 if (gmac->regulator) { in sun8i_dwmac_init()
593 ret = regulator_enable(gmac->regulator); in sun8i_dwmac_init()
600 if (gmac->use_internal_phy) { in sun8i_dwmac_init()
609 if (gmac->regulator) in sun8i_dwmac_init()
610 regulator_disable(gmac->regulator); in sun8i_dwmac_init()
777 struct sunxi_priv_data *gmac = priv->plat->bsp_priv; in get_ephy_nodes() local
798 gmac->ephy_clk = of_clk_get(iphynode, 0); in get_ephy_nodes()
799 if (IS_ERR(gmac->ephy_clk)) in get_ephy_nodes()
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DKconfig61 tristate "Adaptrum Anarion GMAC support"
65 Support for Adaptrum Anarion GMAC Ethernet controller.
106 tristate "MediaTek MT27xx GMAC support"
109 Support for MediaTek GMAC Ethernet controller.
173 tristate "STi GMAC support"
182 SOCs GMAC ethernet controller.
194 SOCs GMAC ethernet controller.
197 tristate "Allwinner GMAC support"
201 Support for Allwinner A20/A31 GMAC ethernet controllers.
205 GMAC ethernet controller.
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Dhwif.c60 /* GMAC older than 3.50 has no extended descriptors */ in stmmac_dwmac1_quirks()
104 bool gmac; member
122 .gmac = false,
140 .gmac = true,
158 .gmac = false,
176 .gmac = false,
194 .gmac = false,
212 .gmac = false,
230 .gmac = false,
249 .gmac = false,
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Ddwmac1000_dma.c3 This is the driver for the GMAC on-chip Ethernet controller for ST SoCs.
142 pr_debug("GMAC: disabling flow control, rxfifo too small(%d)\n", in dwmac1000_configure_fc()
159 pr_debug("GMAC: enable RX store and forward mode\n"); in dwmac1000_dma_operation_mode_rx()
162 pr_debug("GMAC: disable RX SF mode (threshold %d)\n", mode); in dwmac1000_dma_operation_mode_rx()
188 pr_debug("GMAC: enable TX store and forward mode\n"); in dwmac1000_dma_operation_mode_tx()
196 pr_debug("GMAC: disabling TX SF (threshold %d)\n", mode); in dwmac1000_dma_operation_mode_tx()
Ddwmac1000.h22 #define GMAC_DEBUG 0x00000024 /* GMAC debug register */
78 /* GMAC HW ADDR regs */
103 /* GMAC Configuration defines */
132 /* GMAC Frame Filter defines */
147 /* GMAC FLOW CTRL defines */
290 * Be sure that bit 3 in GMAC Register 6 is set for Unicast Pause frame
294 * Be sure that DZPA (bit 7 in Flow Control Register, GMAC Register 6),
/Linux-v6.6/Documentation/devicetree/bindings/net/
Drockchip-dwmac.yaml7 title: Rockchip 10/100/1000 Ethernet driver(GMAC)
18 - rockchip,px30-gmac
19 - rockchip,rk3128-gmac
20 - rockchip,rk3228-gmac
21 - rockchip,rk3288-gmac
22 - rockchip,rk3308-gmac
23 - rockchip,rk3328-gmac
24 - rockchip,rk3366-gmac
25 - rockchip,rk3368-gmac
26 - rockchip,rk3399-gmac
[all …]
Dhisilicon-hix5hd2-gmac.txt1 Hisilicon hix5hd2 gmac controller
5 * "hisilicon,hix5hd2-gmac"
6 * "hisilicon,hi3798cv200-gmac"
7 * "hisilicon,hi3516a-gmac"
9 * "hisilicon,hisi-gmac-v1"
10 * "hisilicon,hisi-gmac-v2"
43 compatible = "hisilicon,hi3798cv200-gmac", "hisilicon,hisi-gmac-v2";
Dallwinner,sun7i-a20-gmac.yaml4 $id: http://devicetree.org/schemas/net/allwinner,sun7i-a20-gmac.yaml#
7 title: Allwinner A20 GMAC
18 const: allwinner,sun7i-a20-gmac
31 - description: GMAC main clock
56 gmac: ethernet@1c50000 {
57 compatible = "allwinner,sun7i-a20-gmac";
Dsnps,dwmac.yaml38 - st,spear600-gmac
51 - allwinner,sun7i-a20-gmac
54 - allwinner,sun8i-r40-gmac
73 - renesas,r9a06g032-gmac
74 - renesas,rzn1-gmac
75 - rockchip,px30-gmac
76 - rockchip,rk3128-gmac
77 - rockchip,rk3228-gmac
78 - rockchip,rk3288-gmac
79 - rockchip,rk3328-gmac
[all …]
Dmediatek-dwmac.yaml21 - mediatek,mt2712-gmac
22 - mediatek,mt8188-gmac
23 - mediatek,mt8195-gmac
35 - mediatek,mt2712-gmac
39 - mediatek,mt8195-gmac
43 - mediatek,mt8188-gmac
44 - const: mediatek,mt8195-gmac
155 compatible = "mediatek,mt2712-gmac", "snps,dwmac-4.20a";
Dipq806x-dwmac.txt8 - compatible: should be "qcom,ipq806x-gmac" along with "snps,dwmac"
20 gmac: ethernet@37000000 {
22 compatible = "qcom,ipq806x-gmac";
/Linux-v6.6/drivers/clk/sunxi/
Dclk-a20-gmac.c19 * sun7i_a20_gmac_clk_setup - Setup function for A20/A31 GMAC clock module
23 * MII TX clock from PHY >-----|___________ _________|----> to GMAC core
24 * GMAC Int. RGMII TX clk >----|___________\__/__gate---|----> to PHY
28 * The external 125 MHz reference is optional, i.e. GMAC can use its
29 * internal TX clock just fine. The A31 GMAC clock module does not have
32 * To keep it simple, let the GMAC use either the MII TX clock for MII mode,
33 * and its internal TX clock for GMII and RGMII modes. The GMAC driver should
36 * Only the GMAC should use this clock. Altering the clock so that it doesn't
37 * match the GMAC's operation parameters will result in the GMAC not being
38 * able to send traffic out. The GMAC driver should set the clock rate and
[all …]
/Linux-v6.6/drivers/net/ethernet/cortina/
Dgemini.h2 /* Register definitions for Gemini GMAC Ethernet device driver
49 * GMAC 0/1 SW TX Q0-5, and GMAC 0/1 HW TX Q0-5
91 /* GMAC 0/1 DMA/TOE register */
145 /* GMAC Hash/Rx/Tx AHB Weighting register */
148 /* TOE GMAC 0/1 register */
332 /* GMAC DMA Control Register
366 /* GMAC Tx Weighting Control Register 0
386 /* GMAC Tx Weighting Control Register 1
410 /* GMAC DMA Tx Description Word 0 Register
434 /* GMAC DMA Tx Description Word 1 Register
[all …]
/Linux-v6.6/drivers/net/ethernet/hisilicon/hns/
Dhns_dsaf_mac.h221 u64 rx_bad_bytes; /* only for gmac */
228 u64 rx_minto64; /* only for gmac */
240 u64 rx_vlan_pkts; /* only for gmac */
241 u64 rx_data_err; /* only for gmac */
242 u64 rx_align_err; /* only for gmac */
243 u64 rx_long_err; /* only for gmac */
253 u64 rx_filter_pkts; /* only for gmac */
254 u64 rx_filter_bytes; /* only for gmac */
255 u64 rx_fifo_overrun_err;/* only for gmac */
256 u64 rx_len_err; /* only for gmac */
[all …]
/Linux-v6.6/Documentation/devicetree/bindings/clock/
Dallwinner,sun7i-a20-gmac-clk.yaml4 $id: http://devicetree.org/schemas/clock/allwinner,sun7i-a20-gmac-clk.yaml#
7 title: Allwinner A20 GMAC TX Clock
18 const: allwinner,sun7i-a20-gmac-clk
45 compatible = "allwinner,sun7i-a20-gmac-clk";
/Linux-v6.6/drivers/pinctrl/sunxi/
Dpinctrl-sun6i-a31.c24 SUNXI_FUNCTION(0x2, "gmac"), /* TXD0 */
32 SUNXI_FUNCTION(0x2, "gmac"), /* TXD1 */
40 SUNXI_FUNCTION(0x2, "gmac"), /* TXD2 */
48 SUNXI_FUNCTION(0x2, "gmac"), /* TXD3 */
56 SUNXI_FUNCTION(0x2, "gmac"), /* TXD4 */
64 SUNXI_FUNCTION(0x2, "gmac"), /* TXD5 */
72 SUNXI_FUNCTION(0x2, "gmac"), /* TXD6 */
80 SUNXI_FUNCTION(0x2, "gmac"), /* TXD7 */
88 SUNXI_FUNCTION(0x2, "gmac"), /* TXCLK */
95 SUNXI_FUNCTION(0x2, "gmac"), /* TXEN */
[all …]
Dpinctrl-sun8i-a83t.c185 SUNXI_FUNCTION(0x4, "gmac")), /* RGMII / MII RXD3 */
190 SUNXI_FUNCTION(0x4, "gmac")), /* RGMII / MII RXD2 */
195 SUNXI_FUNCTION(0x4, "gmac")), /* RGMII / MII RXD1 */
200 SUNXI_FUNCTION(0x4, "gmac")), /* RGMII / MII RXD0 */
205 SUNXI_FUNCTION(0x4, "gmac")), /* RGMII / MII RXCK */
210 SUNXI_FUNCTION(0x4, "gmac")), /* RGMII / MII RXDV */
215 SUNXI_FUNCTION(0x4, "gmac")), /* RGMII / MII RXERR */
220 SUNXI_FUNCTION(0x4, "gmac")), /* RGMII / MII TXD3 */
225 SUNXI_FUNCTION(0x4, "gmac")), /* RGMII / MII TXD2 */
230 SUNXI_FUNCTION(0x4, "gmac")), /* RGMII / MII TXD1 */
[all …]
Dpinctrl-sun9i-a80.c24 SUNXI_FUNCTION(0x2, "gmac"), /* RXD3 */
30 SUNXI_FUNCTION(0x2, "gmac"), /* RXD2 */
36 SUNXI_FUNCTION(0x2, "gmac"), /* RXD1 */
42 SUNXI_FUNCTION(0x2, "gmac"), /* RXD0 */
48 SUNXI_FUNCTION(0x2, "gmac"), /* RXCK */
54 SUNXI_FUNCTION(0x2, "gmac"), /* RXCTL */
60 SUNXI_FUNCTION(0x2, "gmac"), /* RXERR */
66 SUNXI_FUNCTION(0x2, "gmac"), /* TXD3 */
72 SUNXI_FUNCTION(0x2, "gmac"), /* TXD2 */
78 SUNXI_FUNCTION(0x2, "gmac"), /* TXEN */
[all …]
/Linux-v6.6/drivers/net/ethernet/chelsio/cxgb/
Dgmac.h4 * File: gmac.h *
123 struct gmac { struct
129 extern const struct gmac t1_pm3393_ops; argument
130 extern const struct gmac t1_vsc7326_ops;
/Linux-v6.6/net/mac80211/
Daes_gmac.c3 * AES-GMAC for IEEE 802.11 BIP-GMAC-128 and BIP-GMAC-256
/Linux-v6.6/Documentation/networking/device_drivers/ethernet/stmicro/
Dstmmac.rst27 Currently, this network device driver is for all STi embedded MAC/GMAC
46 | Ethernet MAC Universal | N/A | 3.73a | GMAC |
227 GMAC, GMAC4/5 and XGMAC core.
249 GMAC Synopsys(R) chips older than the 3.50. At probe time the driver will
270 Jumbo frames are supported and tested for the GMAC. The GSO has been also
276 TSO (TCP Segmentation Offload) feature is supported by GMAC > 4.x and XGMAC
286 and provide SKB packet to stmmac as it is. The GMAC IP will have to perform
319 Timestamps, new GMAC cores support the advanced timestamp features.
325 New GMAC devices provide own way to manage RGMII/SGMII. This information is
372 7) HW uses the GMAC core::
[all …]
/Linux-v6.6/drivers/net/ethernet/marvell/
Dsky2.h74 P_CLK_REF_LNK1_GM_DIS = 1<<7, /* Disable Clock Ref. Link1 GMAC */
75 P_CLK_COR_LNK1_GM_DIS = 1<<6, /* Disable Clock Core Link1 GMAC */
829 /* Receive GMAC FIFO (YUKON and Yukon-2) */
831 RX_GMF_EA = 0x0c40,/* 32 bit Rx GMAC FIFO End Address */
832 RX_GMF_AF_THR = 0x0c44,/* 32 bit Rx GMAC FIFO Almost Full Thresh. */
833 RX_GMF_CTRL_T = 0x0c48,/* 32 bit Rx GMAC FIFO Control/Test */
834 RX_GMF_FL_MSK = 0x0c4c,/* 32 bit Rx GMAC FIFO Flush Mask */
835 RX_GMF_FL_THR = 0x0c50,/* 16 bit Rx GMAC FIFO Flush Threshold */
836 RX_GMF_FL_CTRL = 0x0c52,/* 16 bit Rx GMAC FIFO Flush Control */
841 RX_GMF_WP = 0x0c60,/* 32 bit Rx GMAC FIFO Write Pointer */
[all …]

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