Searched full:gicv3 (Results 1 – 25 of 48) sorted by relevance
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| /Linux-v5.10/arch/arm64/boot/dts/arm/ |
| D | foundation-v8-gicv3-psci.dts | 4 * ARMv8 Foundation model DTS (GICv3+PSCI configuration)
8 #include "foundation-v8-gicv3.dtsi"
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| D | foundation-v8-gicv3.dts | 5 * ARMv8 Foundation model DTS (GICv3 configuration)
9 #include "foundation-v8-gicv3.dtsi"
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| D | Makefile | 4 foundation-v8-gicv3.dtb foundation-v8-gicv3-psci.dtb
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| D | foundation-v8-gicv3.dtsi | 4 * ARMv8 Foundation model DTS (GICv3 configuration)
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| /Linux-v5.10/include/kvm/ |
| D | arm_vgic.h | 38 VGIC_V3, /* New fancy GICv3 */
121 u32 mpidr; /* GICv3 target VCPU */
208 /* vGIC model the kernel emulates for the guest (GICv2 or GICv3) */
227 /* or a number of GICv3 redistributor regions */
247 * GICv3 spec: IHI 0069E 6.1.1 "LPI Configuration tables"
320 * Members below are used with GICv3 emulation only and represent
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| /Linux-v5.10/Documentation/virt/kvm/devices/ |
| D | arm-vgic-v3.rst | 14 possible to create both a GICv3 and GICv2 on the same VM.
16 Creating a guest GICv3 device requires a host GICv3 as well.
24 Base address in the guest physical address space of the GICv3 distributor
29 Base address in the guest physical address space of the GICv3
96 in the GICv3/4 specs. Getting or setting such a register has the same
147 rules are documented in the GICv3 specification descriptions of the ICPENDR
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| D | arm-vgic-its.rst | 11 optional. Creating a virtual ITS controller also requires a host GICv3 (see
26 Base address in the guest physical address space of the GICv3 ITS
63 The GICV3 must be restored before the ITS and all ITS registers but
70 The expected ordering when restoring the GICv3/ITS is described in section
144 Revision 0 of the ABI only supports the features of a virtual GICv3, and does
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| D | arm-vgic.rst | 16 GICv3 implementations with hardware compatibility support allow creating a
17 guest GICv2 through this interface. For information on creating a guest GICv3
19 create both a GICv3 and GICv2 device on the same VM.
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| /Linux-v5.10/arch/arm64/kvm/vgic/ |
| D | vgic-v3.c | 218 * When emulating GICv3 on GICv3 with SRE=1 on the in vgic_v3_set_vmcr()
250 * When emulating GICv3 on GICv3 with SRE=1 on the in vgic_v3_get_vmcr()
283 * If we are emulating a GICv3, we do it in an non-GICv2-compatible in vgic_v3_enable()
607 kvm_info("GICv3: no GICV resource entry\n"); in vgic_v3_probe()
625 kvm_err("Cannot register GICv3 KVM device.\n"); in vgic_v3_probe()
639 kvm_info("GICv3 sysreg trapping enabled ([%s%s%s], reduced performance)\n", in vgic_v3_probe()
658 * If dealing with a GICv2 emulation on GICv3, VMCR_EL2.VFIQen in vgic_v3_load()
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| D | vgic-init.c | 146 * require prior initialization in case of a virtual GICv3 or trigger in kvm_vgic_dist_init()
225 * If we are creating a VCPU with a GICv3 we must also register the in kvm_vgic_vcpu_init()
390 * is a GICv2. A GICv3 must be explicitly initialized by the guest using the
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| D | vgic-mmio-v2.c | 371 /* GICv3 only uses ICH_AP1Rn for memory mapped (GICv2) guests */ in vgic_mmio_read_apr()
397 /* GICv3 only uses ICH_AP1Rn for memory mapped (GICv2) guests */ in vgic_mmio_write_apr()
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| D | vgic-mmio-v3.c | 304 /* report a GICv3 compliant implementation */ in vgic_mmio_read_v3_idregs()
522 * The GICv3 per-IRQ registers are split to control PPIs and SGIs in the
963 * With GICv3 (and ARE=1) CPUs trigger SGIs by writing to a system register.
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| /Linux-v5.10/Documentation/translations/zh_CN/arm64/ |
| D | booting.txt | 191 对于拥有 GICv3 中断控制器并以 v3 模式运行的系统：
198 - 设备树（DT）或 ACPI 表必须描述一个 GICv3 中断控制器。
200 对于拥有 GICv3 中断控制器并以兼容（v2）模式运行的系统：
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| D | silicon-errata.txt | 74 | Cavium | ThunderX GICv3 | #23154 | CAVIUM_ERRATUM_23154 |
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| /Linux-v5.10/Documentation/devicetree/bindings/interrupt-controller/ |
| D | socionext,synquacer-exiu.txt | 5 level-high type GICv3 SPIs.
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| D | arm,gic-v3.yaml | 13 AArch64 SMP cores are often associated with a GICv3, providing Private
164 GICv3 has one or more Interrupt Translation Services (ITS) that are
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| /Linux-v5.10/Documentation/arm64/ |
| D | booting.rst | 214 For systems with a GICv3 interrupt controller to be used in v3 mode:
228 - The DT or ACPI tables must describe a GICv3 interrupt controller.
230 For systems with a GICv3 interrupt controller to be used in
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| /Linux-v5.10/drivers/irqchip/ |
| D | irq-gic-v3.c | 7 #define pr_fmt(fmt) "GICv3: " fmt
83 * see GICv3/GICv4 Architecture Specification (IHI0069D):
735 /* Extended SPI range, not handled by the GICv2/GICv3 common code */ in gic_dist_init()
1161 "irqchip/arm/gicv3:starting", in gic_smp_init()
1258 .name = "GICv3",
1276 .name = "GICv3",
1544 .desc = "GICv3: Qualcomm MSM8996 broken firmware",
1549 .desc = "GICv3: HIP06 erratum 161010803",
1555 .desc = "GICv3: HIP07 erratum 161010803",
1568 .desc = "GICv3: Cavium erratum 38539",
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| D | irq-gic-v4.c | 17 * intricacies of GICv3, GICv4, and how a guest's view of a GICv3 gets
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| D | irq-gic-common.c | 120 * alone as they are in the redistributor registers on GICv3. in gic_dist_config()
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| /Linux-v5.10/tools/testing/selftests/arm64/fp/ |
| D | README | 76 --irqchip=gicv3. New kvmtool defaults to that if appropriate, but I
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| /Linux-v5.10/arch/arm64/include/asm/ |
| D | arch_gicv3.h | 53 * The gicv3 of ThunderX requires a modified version for reading the
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| /Linux-v5.10/drivers/pci/controller/ |
| D | pcie-iproc.c | 240 * GICv3 ITS)
254 * programed. When ARM GICv3 ITS is used, this should be programmed
1237 * Check if 'msi-map' points to ARM GICv3 ITS, which is the only in iproce_pcie_get_msi()
1245 /* derive GITS_TRANSLATER address from GICv3 */ in iproce_pcie_get_msi()
1300 /* steering MSI to GICv3 ITS */ in iproc_pcie_paxc_v2_msi_steer()
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| /Linux-v5.10/Documentation/devicetree/bindings/pci/ |
| D | brcm,iproc-pcie.txt | 50 On newer iProc platforms, gicv2m or gicv3-its based MSI support should be used
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| /Linux-v5.10/Documentation/devicetree/bindings/misc/ |
| D | fsl,qoriq-mc.txt | 38 For GICv3 and GIC ITS bindings, see:
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