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/Linux-v6.1/Documentation/devicetree/bindings/clock/
Dqcom,gpucc.yaml47 - const: gcc_gpu_gpll0_div_clk_src
81 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
84 "gcc_gpu_gpll0_div_clk_src";
Dqcom,gpucc-sm8350.yaml66 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
/Linux-v6.1/drivers/clk/qcom/
Dgpucc-sdm845.c66 { .fw_name = "gcc_gpu_gpll0_div_clk_src", .name = "gcc_gpu_gpll0_div_clk_src" },
Dgpucc-sc7280.c92 { .fw_name = "gcc_gpu_gpll0_div_clk_src" },
106 { .fw_name = "gcc_gpu_gpll0_div_clk_src", },
Dgpucc-sm8350.c115 { .fw_name = "gcc_gpu_gpll0_div_clk_src" },
129 { .fw_name = "gcc_gpu_gpll0_div_clk_src" },
Dgpucc-sc7180.c66 { .fw_name = "gcc_gpu_gpll0_div_clk_src" },
Dgpucc-sm8250.c78 { .fw_name = "gcc_gpu_gpll0_div_clk_src" },
Dgpucc-sm8150.c75 { .fw_name = "gcc_gpu_gpll0_div_clk_src" },
Dgcc-sc7180.c1156 static struct clk_branch gcc_gpu_gpll0_div_clk_src = { variable
1162 .name = "gcc_gpu_gpll0_div_clk_src",
2287 [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr,
Dgcc-sdm845.c1606 static struct clk_branch gcc_gpu_gpll0_div_clk_src = { variable
1612 .name = "gcc_gpu_gpll0_div_clk_src",
3558 [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr,
3711 [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr,
Dgcc-qcm2290.c1998 static struct clk_branch gcc_gpu_gpll0_div_clk_src = { variable
2004 .name = "gcc_gpu_gpll0_div_clk_src",
2832 [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr,
Dgcc-sm8450.c1396 static struct clk_branch gcc_gpu_gpll0_div_clk_src = { variable
1402 .name = "gcc_gpu_gpll0_div_clk_src",
2991 [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr,
/Linux-v6.1/include/dt-bindings/clock/
Dqcom,gcc-sc7180.h47 #define GCC_GPU_GPLL0_DIV_CLK_SRC 37 macro
Dqcom,gcc-qcm2290.h95 #define GCC_GPU_GPLL0_DIV_CLK_SRC 85 macro
Dqcom,gcc-sm6115.h82 #define GCC_GPU_GPLL0_DIV_CLK_SRC 74 macro
Dqcom,gcc-sc7280.h45 #define GCC_GPU_GPLL0_DIV_CLK_SRC 35 macro
Dqcom,gcc-sm6125.h124 #define GCC_GPU_GPLL0_DIV_CLK_SRC 115 macro
Dqcom,sm6375-gcc.h109 #define GCC_GPU_GPLL0_DIV_CLK_SRC 98 macro
Dqcom,gcc-sm8450.h57 #define GCC_GPU_GPLL0_DIV_CLK_SRC 44 macro
Dqcom,gcc-sdm845.h42 #define GCC_GPU_GPLL0_DIV_CLK_SRC 32 macro
Dqcom,gcc-sm8150.h48 #define GCC_GPU_GPLL0_DIV_CLK_SRC 38 macro
Dqcom,gcc-sm8250.h45 #define GCC_GPU_GPLL0_DIV_CLK_SRC 35 macro
Dqcom,gcc-sm8350.h53 #define GCC_GPU_GPLL0_DIV_CLK_SRC 40 macro
Dqcom,gcc-sc8180x.h47 #define GCC_GPU_GPLL0_DIV_CLK_SRC 37 macro
Dqcom,gcc-sc8280xp.h86 #define GCC_GPU_GPLL0_DIV_CLK_SRC 75 macro

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