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/Linux-v5.10/drivers/fpga/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # FPGA framework configuration
6 menuconfig FPGA config
7 tristate "FPGA Configuration Framework"
10 kernel. The FPGA framework adds a FPGA manager class and FPGA
13 if FPGA
16 tristate "Altera SOCFPGA FPGA Manager"
19 FPGA manager driver support for Altera SOCFPGA.
26 FPGA manager driver support for Altera Arria10 SoCFPGA.
41 tristate "Altera FPGA Passive Serial over SPI"
[all …]
Dts73xx-fpga.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Technologic Systems TS-73xx SBC FPGA loader
7 * FPGA Manager Driver for the on-board Altera Cyclone II FPGA found on
8 * TS-7300, heavily based on load_fpga.c in their vendor tree.
17 #include <linux/fpga/fpga-mgr.h>
44 struct ts73xx_fpga_priv *priv = mgr->priv; in ts73xx_fpga_write_init()
46 /* Reset the FPGA */ in ts73xx_fpga_write_init()
47 writeb(0, priv->io_base + TS73XX_FPGA_CONFIG_REG); in ts73xx_fpga_write_init()
49 writeb(TS73XX_FPGA_RESET, priv->io_base + TS73XX_FPGA_CONFIG_REG); in ts73xx_fpga_write_init()
58 struct ts73xx_fpga_priv *priv = mgr->priv; in ts73xx_fpga_write()
[all …]
/Linux-v5.10/Documentation/fpga/
Ddfl.rst2 FPGA Device Feature List (DFL) Framework Overview
7 - Enno Luebbers <enno.luebbers@intel.com>
8 - Xiao Guangrong <guangrong.xiao@linux.intel.com>
9 - Wu Hao <hao.wu@intel.com>
11 The Device Feature List (DFL) FPGA framework (and drivers according to
14 configure, enumerate, open and access FPGA accelerators on platforms which
16 enables system level management functions such as FPGA reconfiguration.
23 walk through these predefined data structures to enumerate FPGA features:
24 FPGA Interface Unit (FIU), Accelerated Function Unit (AFU) and Private Features,
28 +----------+ +-->+----------+ +-->+----------+ +-->+----------+
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/Linux-v5.10/drivers/watchdog/
Dpika_wdt.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * PIKA FPGA based Watchdog Timer
29 #define DRV_NAME "PIKA-WDT"
50 void __iomem *fpga; member
71 /* -- FPGA: Reset Control Register (32bit R/W) (Offset: 0x14) -- in pikawdt_reset()
76 * Bit 8-11, WTCHDG_TIMEOUT_SEC: Sets the watchdog timeout value in in pikawdt_reset()
80 unsigned reset = in_be32(pikawdt_private.fpga + 0x14); in pikawdt_reset()
81 /* enable with max timeout - 15 seconds */ in pikawdt_reset()
83 out_be32(pikawdt_private.fpga + 0x14, reset); in pikawdt_reset()
118 return -EBUSY; in pikawdt_open()
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/Linux-v5.10/drivers/staging/gs_fpgaboot/
DREADME2 Linux Driver Source for Xilinx FPGA firmware download
16 - Download Xilinx FPGA firmware
17 - This module downloads Xilinx FPGA firmware using gpio pins.
21 An FPGA (Field Programmable Gate Array) is a programmable hardware that is
24 This driver provides a way to download FPGA firmware.
28 - load Xilinx FPGA bitstream format[1] firmware image file using
30 - program the Xilinx FPGA using SelectMAP (parallel) mode [2]
31 - FPGA prgram is done by gpio based bit-banging, as an example
32 - platform independent file: gs_fpgaboot.c
33 - platform dependent file: io.c
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/Linux-v5.10/Documentation/driver-api/
Dxillybus.rst2 Xillybus driver for generic FPGA interface
10 - Introduction
11 -- Background
12 -- Xillybus Overview
14 - Usage
15 -- User interface
16 -- Synchronization
17 -- Seekable pipes
19 - Internals
20 -- Source code organization
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Dmen-chameleon-bus.rst30 ----------------------
34 based devices.
37 -----------------------------------------
39 The current implementation is limited to PCI and PCIe based carrier devices
43 - Multi-resource MCB devices like the VME Controller or M-Module carrier.
44 - MCB devices that need another MCB device, like SRAM for a DMA Controller's
46 - A per-carrier IRQ domain for carrier devices that have one (or more) IRQs
47 per MCB device like PCIe based carriers with MSI or MSI-X support.
54 - The MEN Chameleon Bus itself,
55 - drivers for MCB Carrier Devices and
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/Linux-v5.10/arch/powerpc/boot/
Debony.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Based on earlier code:
9 * Copyright 2002-2005 MontaVista Software Inc.
30 #define EBONY_FPGA_PATH "/plb/opb/ebc/fpga"
32 #define EBONY_SMALL_FLASH_PATH "/plb/opb/ebc/small-flash"
38 u8 *fpga; in ebony_flashsel_fixup() local
43 fatal("Couldn't locate FPGA node %s\n\r", EBONY_FPGA_PATH); in ebony_flashsel_fixup()
45 if (getprop(devp, "virtual-reg", &fpga, sizeof(fpga)) != sizeof(fpga)) in ebony_flashsel_fixup()
46 fatal("%s has missing or invalid virtual-reg property\n\r", in ebony_flashsel_fixup()
49 fpga_reg0 = in_8(fpga); in ebony_flashsel_fixup()
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/Linux-v5.10/drivers/mcb/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
13 FPGA based devices. It is used to identify MCB based IP-Cores within
14 an FPGA and provide the necessary framework for instantiating drivers
21 tristate "PCI based MCB carrier"
26 This is a MCB carrier on a PCI device. Both PCI attached on-board
30 If build as a module, the module is called mcb-pci.ko
33 tristate "LPC (non PCI) based MCB carrier"
39 If build as a module, the module is called mcb-lpc.ko
/Linux-v5.10/include/uapi/linux/
Dfpga-dfl.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
3 * Header File for FPGA DFL User API
5 * Copyright (C) 2017-2018 Intel Corporation, Inc.
23 * The IOCTL interface for DFL based FPGA is designed for extensibility by
38 * DFL_FPGA_GET_API_VERSION - _IO(DFL_FPGA_MAGIC, DFL_FPGA_BASE + 0)
47 * DFL_FPGA_CHECK_EXTENSION - _IO(DFL_FPGA_MAGIC, DFL_FPGA_BASE + 1)
58 * DFL_FPGA_PORT_RESET - _IO(DFL_FPGA_MAGIC, DFL_PORT_BASE + 0)
60 * Reset the FPGA Port and its AFU. No parameters are supported.
64 * Return: 0 on success, -errno of failure
70 * DFL_FPGA_PORT_GET_INFO - _IOR(DFL_FPGA_MAGIC, DFL_PORT_BASE + 1,
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/Linux-v5.10/arch/powerpc/boot/dts/fsl/
Dgef_ppc9a.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Based on: SBS CM6 Device Tree Source
14 * Compiled with dtc -I dts -O dtb -o gef_ppc9a.dtb gef_ppc9a.dts
17 /include/ "mpc8641si-pre.dtsi"
35 4 0 0xfc000000 0x00008000 // FPGA
36 5 0 0xfc008000 0x00008000 // AFIX FPGA
37 6 0 0xfd000000 0x00800000 // IO FPGA (8-bit)
38 7 0 0xfd800000 0x00800000>; // IO FPGA (32-bit)
42 compatible = "gef,ppc9a-firmware-mirror", "cfi-flash";
44 bank-width = <4>;
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Dgef_sbc310.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Based on: SBS CM6 Device Tree Source
14 * Compiled with dtc -I dts -O dtb -o gef_sbc310.dtb gef_sbc310.dts
17 /include/ "mpc8641si-pre.dtsi"
35 4 0 0xfc000000 0x00010000>; // FPGA
39 compatible = "gef,sbc310-firmware-mirror", "cfi-flash";
41 bank-width = <2>;
42 device-width = <2>;
43 #address-cells = <1>;
44 #size-cells = <1>;
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Dgef_sbc610.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Based on: SBS CM6 Device Tree Source
14 * Compiled with dtc -I dts -O dtb -o gef_sbc610.dtb gef_sbc610.dts
17 /include/ "mpc8641si-pre.dtsi"
35 4 0 0xfc000000 0x00008000 // FPGA
36 5 0 0xfc008000 0x00008000 // AFIX FPGA
37 6 0 0xfd000000 0x00800000 // IO FPGA (8-bit)
38 7 0 0xfd800000 0x00800000>; // IO FPGA (32-bit)
42 compatible = "gef,sbc610-firmware-mirror", "cfi-flash";
44 bank-width = <4>;
[all …]
Dge_imp3a.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright 2010-2011 GE Intelligent Platforms Embedded Systems, Inc.
7 * Based on: P2020 DS Device Tree Source
11 /include/ "p2020si-pre.dtsi"
35 #address-cells = <1>;
36 #size-cells = <1>;
37 compatible = "ge,imp3a-firmware-mirror", "cfi-flash";
39 bank-width = <2>;
40 device-width = <1>;
45 read-only;
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/Linux-v5.10/drivers/media/pci/cx23885/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
48 This is a video4linux driver for Conexant 23885 based
55 tristate "Altera FPGA based CI module"
59 An Altera FPGA CI module for NetUP Dual DVB-T/C RF CI card.
62 module will be called altera-ci
/Linux-v5.10/Documentation/devicetree/bindings/net/
Dmdio-mux-multiplexer.txt5 producer, gpio mux producer or generic register based mux producer.
9 - compatible : should be "mmio-mux-multiplexer"
10 - mux-controls : mux controller node to use for operating the mux
11 - mdio-parent-bus : phandle to the parent MDIO bus.
17 Documentation/devicetree/bindings/mux/mux-controller.txt
18 and Documentation/devicetree/bindings/net/mdio-mux.txt
24 fpga@66 { // fpga connected to i2c
25 compatible = "fsl,lx2160aqds-fpga", "fsl,fpga-qixis-i2c",
26 "simple-mfd";
29 mux: mux-controller { // Mux Producer
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/Linux-v5.10/arch/powerpc/platforms/86xx/
Dgef_sbc610.c1 // SPDX-License-Identifier: GPL-2.0-or-later
9 * Based on: mpc86xx_hpcn.c (MPC86xx HPCN board specific routines)
12 * NEC fixup adapted from arch/mips/pci/fixup-lm2e.c
25 #include <asm/pci-bridge.h>
56 * There is a simple interrupt handler in the main FPGA, this needs in gef_sbc610_init_irq()
59 cascade_node = of_find_compatible_node(NULL, NULL, "gef,fpga-pic"); in gef_sbc610_init_irq()
61 printk(KERN_WARNING "SBC610: No FPGA PIC\n"); in gef_sbc610_init_irq()
82 regs = of_find_compatible_node(NULL, NULL, "gef,fpga-regs"); in gef_sbc610_setup_arch()
113 /* Return the FPGA revision */
129 ('A' + gef_sbc610_get_board_rev() - 1)); in gef_sbc610_show_cpuinfo()
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Dgef_ppc9a.c1 // SPDX-License-Identifier: GPL-2.0-or-later
9 * Based on: mpc86xx_hpcn.c (MPC86xx HPCN board specific routines)
12 * NEC fixup adapted from arch/mips/pci/fixup-lm2e.c
25 #include <asm/pci-bridge.h>
56 * There is a simple interrupt handler in the main FPGA, this needs in gef_ppc9a_init_irq()
59 cascade_node = of_find_compatible_node(NULL, NULL, "gef,fpga-pic-1.00"); in gef_ppc9a_init_irq()
61 printk(KERN_WARNING "PPC9A: No FPGA PIC\n"); in gef_ppc9a_init_irq()
82 regs = of_find_compatible_node(NULL, NULL, "gef,ppc9a-fpga-regs"); in gef_ppc9a_setup_arch()
113 /* Return the FPGA revision */
148 seq_printf(m, "FPGA Revision\t: %u\n", gef_ppc9a_get_fpga_rev()); in gef_ppc9a_show_cpuinfo()
[all …]
Dgef_sbc310.c1 // SPDX-License-Identifier: GPL-2.0-or-later
9 * Based on: mpc86xx_hpcn.c (MPC86xx HPCN board specific routines)
12 * NEC fixup adapted from arch/mips/pci/fixup-lm2e.c
25 #include <asm/pci-bridge.h>
56 * There is a simple interrupt handler in the main FPGA, this needs in gef_sbc310_init_irq()
59 cascade_node = of_find_compatible_node(NULL, NULL, "gef,fpga-pic"); in gef_sbc310_init_irq()
61 printk(KERN_WARNING "SBC310: No FPGA PIC\n"); in gef_sbc310_init_irq()
81 regs = of_find_compatible_node(NULL, NULL, "gef,fpga-regs"); in gef_sbc310_setup_arch()
121 /* Return the FPGA revision */
138 ('A' + gef_sbc310_get_board_rev() - 1)); in gef_sbc310_show_cpuinfo()
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/Linux-v5.10/drivers/irqchip/
Dirq-versatile-fpga.c1 // SPDX-License-Identifier: GPL-2.0
3 * Support for Versatile FPGA-based IRQ controllers
10 #include <linux/irqchip/versatile-fpga.h>
35 * struct fpga_irq_data - irq data container for the FPGA IRQ controller
57 u32 mask = 1 << d->hwirq; in fpga_irq_mask()
59 writel(mask, f->base + IRQ_ENABLE_CLEAR); in fpga_irq_mask()
65 u32 mask = 1 << d->hwirq; in fpga_irq_unmask()
67 writel(mask, f->base + IRQ_ENABLE_SET); in fpga_irq_unmask()
78 status = readl(f->base + IRQ_STATUS); in fpga_irq_handle()
85 unsigned int irq = ffs(status) - 1; in fpga_irq_handle()
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/Linux-v5.10/arch/powerpc/platforms/52xx/
Dmedia5200.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Support for 'media5200-platform' compatible boards.
11 * Notable characteristic of the Media5200 is the presence of an FPGA
29 { .compatible = "fsl,mpc5200-gpio", },
30 { .compatible = "mpc5200-gpio", },
34 /* FPGA register set */
38 #define MEDIA5200_IRQ_SHIFT (32 - MEDIA5200_NUM_IRQS)
72 .name = "Media5200 FPGA",
85 raw_spin_lock(&desc->lock); in media5200_irq_cascade()
86 chip->irq_mask(&desc->irq_data); in media5200_irq_cascade()
[all …]
/Linux-v5.10/drivers/net/ethernet/mellanox/mlx5/core/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
16 Core driver for low level functionality of the ConnectX-4 and
17 Connect-IB cards by Mellanox Technologies.
29 and an FPGA chip on one board. If you select this option, the
30 mlx5_core driver will include the Innova FPGA core and allow building
31 sandbox-specific client drivers.
40 Ethernet support in Mellanox Technologies ConnectX-4 NIC.
47 Mellanox MLX5 ethernet hardware-accelerated receive flow steering support,
65 Mellanox Technologies Ethernet Multi-Physical Function Switch (MPFS)
66 support in ConnectX NIC. MPFs is required for when multi-PF configuration
[all …]
/Linux-v5.10/arch/powerpc/platforms/85xx/
Dge_imp3a.c1 // SPDX-License-Identifier: GPL-2.0-or-later
9 * Based on: mpc85xx_ds.c (MPC85xx DS Board Setup)
24 #include <asm/pci-bridge.h>
47 if (of_machine_is_compatible("fsl,MPC8572DS-CAMP")) { in ge_imp3a_pic_init()
63 * There is a simple interrupt handler in the main FPGA, this needs in ge_imp3a_pic_init()
66 for_each_node_by_type(np, "interrupt-controller") in ge_imp3a_pic_init()
67 if (of_device_is_compatible(np, "gef,fpga-pic-1.00")) { in ge_imp3a_pic_init()
73 printk(KERN_WARNING "IMP3A: No FPGA PIC\n"); in ge_imp3a_pic_init()
88 if (of_device_is_compatible(np, "fsl,mpc8540-pci") || in ge_imp3a_pci_assign_primary()
89 of_device_is_compatible(np, "fsl,mpc8548-pcie") || in ge_imp3a_pci_assign_primary()
[all …]
Dsocrates.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Based on MPC8560 ADS and arch/ppc tqm85xx ports
12 * Copyright (c) 2005-2006 DENX Software Engineering
15 * Based on original work by
30 #include <asm/pci-bridge.h>
51 np = of_find_compatible_node(NULL, NULL, "abb,socrates-fpga-pic"); in socrates_pic_init()
53 printk(KERN_ERR "Could not find socrates-fpga-pic node\n"); in socrates_pic_init()
74 * Called very early, device-tree isn't unflattened
/Linux-v5.10/Documentation/devicetree/bindings/fpga/
Dfpga-region.txt1 FPGA Region Device Tree Binding
6 - Introduction
7 - Terminology
8 - Sequence
9 - FPGA Region
10 - Supported Use Models
11 - Device Tree Examples
12 - Constraints
18 FPGA Regions represent FPGA's and partial reconfiguration regions of FPGA's in
19 the Device Tree. FPGA Regions provide a way to program FPGAs under device tree
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