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/Linux-v5.15/arch/arm/kernel/
Dfiq.c3 * linux/arch/arm/kernel/fiq.c
8 * FIQ support written by Philip Blundell <philb@gnu.org>, 1998.
10 * FIQ support re-written by Russell King to be more generic
12 * We now properly support a method by which the FIQ handlers can
14 * the FIQ vector itself.
17 * 1. Owner A claims FIQ:
22 * - enables FIQ.
23 * 3. Owner B claims FIQ:
31 * - enables FIQ.
32 * 5. Owner B releases FIQ:
[all …]
Dfiqasm.S4 * Derived from code originally in linux/arch/arm/kernel/fiq.c:
10 * FIQ support written by Philip Blundell <philb@gnu.org>, 1998.
12 * FIQ support re-written by Russell King to be more generic
21 * Taking an interrupt in FIQ mode is death, so both these functions
28 msr cpsr_c, r2 @ select FIQ mode
41 msr cpsr_c, r2 @ select FIQ mode
/Linux-v5.15/fs/fuse/
Ddev.c195 u64 fuse_get_unique(struct fuse_iqueue *fiq) in fuse_get_unique() argument
197 fiq->reqctr += FUSE_REQ_ID_STEP; in fuse_get_unique()
198 return fiq->reqctr; in fuse_get_unique()
208 * A new request is available, wake fiq->waitq
210 static void fuse_dev_wake_and_unlock(struct fuse_iqueue *fiq) in fuse_dev_wake_and_unlock() argument
211 __releases(fiq->lock) in fuse_dev_wake_and_unlock()
213 wake_up(&fiq->waitq); in fuse_dev_wake_and_unlock()
214 kill_fasync(&fiq->fasync, SIGIO, POLL_IN); in fuse_dev_wake_and_unlock()
215 spin_unlock(&fiq->lock); in fuse_dev_wake_and_unlock()
225 static void queue_request_and_unlock(struct fuse_iqueue *fiq, in queue_request_and_unlock() argument
[all …]
/Linux-v5.15/arch/arm/mach-omap1/
Dams-delta-fiq.c3 * Amstrad E3 FIQ handling
20 #include <linux/platform_data/ams-delta-fiq.h>
23 #include <asm/fiq.h>
25 #include "ams-delta-fiq.h"
29 .name = "ams-delta-fiq"
33 * This buffer is shared between FIQ and IRQ contexts.
34 * The FIQ and IRQ isrs can both read and write it.
36 * followed by the circular buffer where the FIQ isr stores
38 * <linux/platform_data/ams-delta-fiq.h> for details of offsets.
58 * until the IRQ counter catches the FIQ incremented interrupt counter. in deferred_fiq()
[all …]
Dams-delta-fiq-handler.S3 * linux/arch/arm/mach-omap1/ams-delta-fiq-handler.S
14 #include <linux/platform_data/ams-delta-fiq.h>
20 #include "ams-delta-fiq.h"
92 @ FIQ intrrupt handler
99 beq exit @ none - spurious FIQ? exit
103 mov r8, #2 @ reset FIQ agreement
113 subs pc, lr, #4 @ return from FIQ
137 @ Keyboard clock FIQ mode interrupt handler
221 @ Hook switch interrupt FIQ mode simple handler
238 @ Modem FIQ mode interrupt handler stub
[all …]
Dirq.c98 * NOTE: There is currently no OMAP fiq handler for Linux. Read the
99 * mailing list threads on FIQ handlers if you are planning to
100 * add a FIQ handler for OMAP.
102 static void omap_irq_set_cfg(int irq, int fiq, int priority, int trigger) in omap_irq_set_cfg() argument
108 /* FIQ is only available on bank 0 interrupts */ in omap_irq_set_cfg()
109 fiq = bank ? 0 : (fiq & 0x1); in omap_irq_set_cfg()
110 val = fiq | ((priority & 0x1f) << 2) | ((trigger & 0x1) << 1); in omap_irq_set_cfg()
Dams-delta-fiq.h4 * arch/arm/mach-omap1/ams-delta-fiq.h
6 * Taken from the original Amstrad modifications to fiq.h
22 * Interrupt number used for passing control from FIQ to IRQ.
/Linux-v5.15/drivers/spi/
Dspi-s3c24xx.c22 #include <linux/spi/s3c24xx-fiq.h>
25 #include <asm/fiq.h>
212 /* Support for FIQ based pseudo-DMA to improve the transfer speed.
215 * used by the FIQ core to move data between main memory and the peripheral
221 * struct spi_fiq_code - FIQ code and header
224 * @data: The code itself to install as a FIQ handler.
233 * s3c24xx_spi_tryfiq - attempt to claim and setup FIQ for transfer
236 * Claim the FIQ handler (only one can be active at any one time) and
241 * as normal, since the IRQ will have been re-routed to the FIQ handler.
252 /* try and claim fiq if we haven't got it, and if not in s3c24xx_spi_tryfiq()
[all …]
/Linux-v5.15/arch/arm/include/asm/
Dfiq.h3 * arch/arm/include/asm/fiq.h
5 * Support for FIQ on ARM architectures.
9 * NOTE: The FIQ mode registers are not magically preserved across
28 * reacquire FIQ
40 extern void enable_fiq(int fiq);
41 extern void disable_fiq(int fiq);
Decard.h104 unsigned char fiqmask; /* FIQ mask */
106 unsigned long fiqoff; /* FIQ offset */
147 void __iomem *fiqaddr; /* address of FIQ register */
149 unsigned char fiqmask; /* FIQ mask */
154 void *fiq_data; /* Data for use for FIQ by card */
160 CONST unsigned int fiq; /* FIQ number (for request_irq) */ member
/Linux-v5.15/include/linux/irqchip/
Dirq-bcm2836.h13 * next 2 bits identify the CPU that the GPU FIQ goes to.
22 * next 4 bits are the CPU's timer FIQ enables (which override the IRQ
28 * the next 4 bits are the CPU's per-mailbox FIQ enables (which
37 /* Same status bits as above, but for FIQ. */
/Linux-v5.15/Documentation/devicetree/bindings/interrupt-controller/
Dcirrus,clps711x-intc.txt14 1: BLINT Battery low (FIQ)
15 3: MCINT Media changed (FIQ)
33 32: DAIINT DAI interface (FIQ)
/Linux-v5.15/drivers/irqchip/
Dirq-apple-aic.c36 * - FIQ hwirq numbers are assigned after true hwirqs, and are per-cpu.
39 * - <1 nr flags> - FIQ #nr
108 * IMP-DEF sysregs that control FIQ sources
138 /* Guest timer FIQ enable register */
162 * FIQ hwirq index definitions: FIQ sources use the DT binding defines
305 * FIQ irqchip
376 * the FIQ source state without having to peek down into sources... in aic_handle_fiq()
385 * Since not dealing with any of these results in a FIQ storm, in aic_handle_fiq()
423 pr_err_ratelimited("PMC FIQ fired. Masking.\n"); in aic_handle_fiq()
431 pr_err_ratelimited("Uncore PMC FIQ fired. Masking.\n"); in aic_handle_fiq()
[all …]
Dirq-ixp4xx.c29 #define IXP4XX_ICLR 0x08 /* Interrupt IRQ/FIQ Select */
31 #define IXP4XX_ICFP 0x10 /* FIQ Status */
34 #define IXP4XX_ICFH 0x1C /* FIQ Highest Pri Int */
39 #define IXP4XX_ICLR2 0x28 /* Interrupt IRQ/FIQ Select 2 */
41 #define IXP4XX_ICFP2 0x30 /* FIQ Status */
265 /* Route all sources to IRQ instead of FIQ */ in ixp4xx_irq_setup()
272 /* Route upper 32 sources to IRQ instead of FIQ */ in ixp4xx_irq_setup()
Dirq-st.c104 /* Select IRQ/FIQ channel for device. */ in st_irq_xlate()
125 channels = of_property_count_u32_elems(np, "st,fiq-device"); in st_irq_syscfg_enable()
127 dev_err(&pdev->dev, "st,enable-fiq-device must have 2 elems\n"); in st_irq_syscfg_enable()
138 of_property_read_u32_index(np, "st,fiq-device", i, &device); in st_irq_syscfg_enable()
/Linux-v5.15/tools/testing/selftests/kvm/lib/aarch64/
Dhandlers.S110 HANDLER_INVALID // FIQ EL1t
115 HANDLER el1h_fiq // FIQ EL1h
120 HANDLER el0_fiq_64 // FIQ 64-bit EL0
125 HANDLER el0_fiq_32 // FIQ 32-bit EL0
/Linux-v5.15/arch/arm64/kernel/
Dhibernate-asm.S148 ventry el2_fiq_invalid // FIQ EL2t
153 ventry el2_fiq_invalid // FIQ EL2h
158 ventry el1_fiq_invalid // FIQ 64-bit EL1
163 ventry el1_fiq_invalid // FIQ 32-bit EL1
Dirq.c81 panic("FIQ taken without a root FIQ handler\n"); in default_handle_fiq()
103 pr_info("Root FIQ handler: %ps\n", handle_fiq); in set_handle_fiq()
Dhyp-stub.S27 ventry el2_fiq_invalid // FIQ EL2t
32 ventry el2_fiq_invalid // FIQ EL2h
37 ventry el1_fiq_invalid // FIQ 64-bit EL1
42 ventry el1_fiq_invalid // FIQ 32-bit EL1
/Linux-v5.15/arch/arm/mach-mmp/
Dregs-icu.h25 #define ICU_AP_FIQ_SEL_INT_NUM ICU_REG(0x108) /* AP FIQ Selected Interrupt */
34 * IRQ0/FIQ0 is routed to SP IRQ/FIQ.
35 * IRQ1 is routed to PJ4 IRQ, and IRQ2 is routes to PJ4 FIQ.
/Linux-v5.15/arch/arm/mach-s3c/
Dirq-s3c24xx-fiq.S7 * S3C24XX SPI - FIQ pseudo-DMA transfer code
16 #include <linux/spi/s3c24xx-fiq.h>
24 @ defined in fiq.h so that they can be shared with the C files which
/Linux-v5.15/arch/arm/mach-rpc/
Ddma.c17 #include <asm/fiq.h>
262 unsigned int fiq; member
290 printk("floppydma: couldn't claim FIQ.\n"); in floppy_enable_dma()
296 enable_fiq(fdma->fiq); in floppy_enable_dma()
302 disable_fiq(fdma->fiq); in floppy_disable_dma()
339 .fiq = FIQ_FLOPPYDATA,
/Linux-v5.15/arch/arm64/include/asm/
Dirqflags.h15 * FIQ exceptions, in the 'daif' register. We mask and unmask them in 'daif'
18 * Masking SError masks IRQ/FIQ, but not debug exceptions. IRQ and FIQ are
/Linux-v5.15/arch/arm64/kvm/hyp/
Dhyp-entry.S172 invalid_vect el2t_fiq_invalid // FIQ EL2t
177 invalid_vect el2h_fiq_invalid // FIQ EL2h
182 valid_vect el1_fiq // FIQ 64-bit EL1
187 valid_vect el1_fiq // FIQ 32-bit EL1
/Linux-v5.15/arch/arm64/kvm/hyp/nvhe/
Dhyp-init.S28 ventry __invalid // FIQ EL2t
33 ventry __invalid // FIQ EL2h
38 ventry __invalid // FIQ 64-bit EL1
43 ventry __invalid // FIQ 32-bit EL1

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