Searched full:ete (Results 1 – 17 of 17) sorted by relevance
5 $id: "http://devicetree.org/schemas/arm/ete.yaml#"15 Arm Embedded Trace Extension(ETE) is a per CPU trace component that18 The trace generated by the ETE could be stored via legacy CoreSight20 Arm Trace Buffer Extension (TRBE)). Since the ETE can be connected to27 pattern: "^ete([0-9a-f]+)$"34 Handle to the cpu this ETE is bound to.39 Output connections from the ETE to legacy CoreSight trace bus.43 description: Output connection from the ETE to legacy CoreSight Trace bus.54 # An ETE node without legacy CoreSight connections60 # An ETE node with legacy CoreSight connections
101 tristate "CoreSight ETMv4.x / ETE driver"107 version 4.x and the Embedded Trace Extensions (ETE). Both are CPU tracer183 TRBE always needs to be used along with it's corresponding percpu ETE184 component. ETE generates trace data which is then captured with TRBE.186 system registers. But it's explicit dependency with trace unit (ETE)
5 * device (ETE) thus generating required trace data. Trace can be enabled28 * sinks and thus we use ETE trace packets to pad the36 * This is about 44bytes of ETE trace. To be on196 * The ETE trace has alignment synchronization packets allowing in trbe_snapshot_offset()
127 pr_warn_ratelimited("ete: trying to read unsupported register @%x\n", in ete_sysreg_read()147 pr_warn_ratelimited("ete: trying to write to unsupported register @%x\n", in ete_sysreg_write()439 * ETE mandates that the TRCRSR is written to before in etm4_enable_hw()1931 type_name = "ete"; in etm4_probe()1932 /* ETE v1 has major version == 0b101. Adjust this for logging.*/ in etm4_probe()
2382 * Common registers to ETE & ETM4x accessible via system in etm4x_register_implemented()2389 * We only support etm4x and ete. So if the device is not in etm4x_register_implemented()2390 * ETE, it must be ETMv4x. in etm4x_register_implemented()2403 * Also ETE doesn't implement memory mapped access, thus in etm4x_register_implemented()
404 /* ETE only supports system register access */
16 generators (ETE), are plugged in as source device.19 driven via the CoreSight driver framework to support the ETE (which is
164 config->reg_configr = params->ete.reg_configr; in cs_etm_decoder__gen_ete_config()165 config->reg_traceidr = params->ete.reg_traceidr; in cs_etm_decoder__gen_ete_config()166 config->reg_idr0 = params->ete.reg_idr0; in cs_etm_decoder__gen_ete_config()167 config->reg_idr1 = params->ete.reg_idr1; in cs_etm_decoder__gen_ete_config()168 config->reg_idr2 = params->ete.reg_idr2; in cs_etm_decoder__gen_ete_config()169 config->reg_idr8 = params->ete.reg_idr8; in cs_etm_decoder__gen_ete_config()170 config->reg_devarch = params->ete.reg_devarch; in cs_etm_decoder__gen_ete_config()
55 struct cs_ete_trace_params ete; member
538 int etmv3 = 0, etmv4 = 0, ete = 0; in cs_etm_info_priv_size() local550 ete++; in cs_etm_info_priv_size()563 ete++; in cs_etm_info_priv_size()574 (ete * CS_ETE_PRIV_SIZE) + in cs_etm_info_priv_size()632 * ETE if ARCHVER is 5 (ARCHVER is 4 for ETM) and ARCHPART is 0xA13. in cs_etm_is_ete()673 /* ETE uses the same registers as ETMv4 plus TRCDEVARCH */ in cs_etm_get_metadata()
469 t_params[idx].ete.reg_idr0 = metadata[idx][CS_ETMV4_TRCIDR0]; in cs_etm__set_trace_param_ete()470 t_params[idx].ete.reg_idr1 = metadata[idx][CS_ETMV4_TRCIDR1]; in cs_etm__set_trace_param_ete()471 t_params[idx].ete.reg_idr2 = metadata[idx][CS_ETMV4_TRCIDR2]; in cs_etm__set_trace_param_ete()472 t_params[idx].ete.reg_idr8 = metadata[idx][CS_ETMV4_TRCIDR8]; in cs_etm__set_trace_param_ete()473 t_params[idx].ete.reg_configr = metadata[idx][CS_ETMV4_TRCCONFIGR]; in cs_etm__set_trace_param_ete()474 t_params[idx].ete.reg_traceidr = metadata[idx][CS_ETMV4_TRCTRACEIDR]; in cs_etm__set_trace_param_ete()475 t_params[idx].ete.reg_devarch = metadata[idx][CS_ETE_TRCDEVARCH]; in cs_etm__set_trace_param_ete()2604 * ETE and ETMv4 can be printed in the same block because the number of parameters in cs_etm__print_cpu_metadata_v1()2605 * is saved and they share the list of parameter names. ETE is also only supported in cs_etm__print_cpu_metadata_v1()2982 /* ETE shares first part of metadata with ETMv4 */ in cs_etm__process_auxtrace_info()
80 * ETE metadata is ETMv4 plus TRCDEVARCH register and doesn't support header V0 since it was
622 | if (ete =$7fff) then INF or NAN628 | if (ete = $0000) then
997 * is enabled (ETE).1005 * enabled (ETE).
1298 /* xhci 1.1 uses the TD_SIZE field for TBC if Extended TBC is enabled (ETE) */1303 /* Total burst count field, Rsvdz on xhci 1.1 with Extended TBC enabled (ETE) */
4110 /* xhci 1.1 with ETE uses TD_Size field for TBC, old is Rsvdz */ in xhci_queue_isoc_tx()4152 /* xhci 1.1 with ETE uses TD Size field for TBC */ in xhci_queue_isoc_tx()
1856 F: Documentation/devicetree/bindings/arm/ete.yaml
