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/Linux-v5.15/drivers/net/ethernet/broadcom/
Dbcm4908_enet.c82 static u32 enet_read(struct bcm4908_enet *enet, u16 offset) in enet_read() argument
84 return readl(enet->base + offset); in enet_read()
87 static void enet_write(struct bcm4908_enet *enet, u16 offset, u32 value) in enet_write() argument
89 writel(value, enet->base + offset); in enet_write()
92 static void enet_maskset(struct bcm4908_enet *enet, u16 offset, u32 mask, u32 set) in enet_maskset() argument
98 val = enet_read(enet, offset); in enet_maskset()
100 enet_write(enet, offset, val); in enet_maskset()
103 static void enet_set(struct bcm4908_enet *enet, u16 offset, u32 set) in enet_set() argument
105 enet_maskset(enet, offset, set, set); in enet_set()
108 static u32 enet_umac_read(struct bcm4908_enet *enet, u16 offset) in enet_umac_read() argument
[all …]
/Linux-v5.15/drivers/net/ethernet/brocade/bna/
Dbna_enet.c17 if (ethport->bna->enet.type == BNA_ENET_T_REGULAR) in ethport_can_be_up()
150 bna_bfi_pause_set_rsp(struct bna_enet *enet, struct bfi_msgq_mhdr *msghdr) in bna_bfi_pause_set_rsp() argument
152 bfa_fsm_send_event(enet, ENET_E_FWRESP_PAUSE); in bna_bfi_pause_set_rsp()
342 bna_bfi_pause_set_rsp(&bna->enet, msghdr); in bna_msgq_rsp_handler()
390 cbfn(&(_ethport)->bna->enet); \
448 lpbk_up_req->mode = (ethport->bna->enet.type == in bna_bfi_ethport_lpbk_up()
479 if (ethport->bna->enet.type == BNA_ENET_T_REGULAR) in bna_bfi_ethport_up()
488 if (ethport->bna->enet.type == BNA_ENET_T_REGULAR) in bna_bfi_ethport_down()
753 bna_enet_cb_ethport_stopped(struct bna_enet *enet) in bna_enet_cb_ethport_stopped() argument
755 bfa_wc_down(&enet->chld_stop_wc); in bna_enet_cb_ethport_stopped()
[all …]
Dbna.h300 /* APIs for ENET */
337 /* APIs for ENET */
375 /* ENET */
378 int bna_enet_mtu_get(struct bna_enet *enet);
381 void bna_enet_cb_tx_stopped(struct bna_enet *enet);
382 void bna_enet_cb_rx_stopped(struct bna_enet *enet);
385 void bna_enet_enable(struct bna_enet *enet);
386 void bna_enet_disable(struct bna_enet *enet, enum bna_cleanup_type type,
388 void bna_enet_pause_config(struct bna_enet *enet,
390 void bna_enet_mtu_set(struct bna_enet *enet, int mtu,
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/Linux-v5.15/arch/arm/boot/dts/
Dlpc4337-ciaa.dts40 enet_rmii_pins: enet-rmii-pins {
43 function = "enet";
52 function = "enet";
61 function = "enet";
69 function = "enet";
77 function = "enet";
86 function = "enet";
94 function = "enet";
Dlpc4350-hitex-eval.dts239 enet_mii_pins: enet-mii-pins {
242 function = "enet";
249 function = "enet";
255 function = "enet";
262 function = "enet";
269 function = "enet";
276 function = "enet";
283 function = "enet";
Dlpc4357-myd-lpc4357.dts193 enet_rmii_pins: enet-rmii-pins {
196 function = "enet";
205 function = "enet";
212 function = "enet";
220 function = "enet";
228 function = "enet";
235 function = "enet";
241 function = "enet";
Dlpc4357-ea4357-devkit.dts269 enet_rmii_pins: enet-rmii-pins {
272 function = "enet";
281 function = "enet";
290 function = "enet";
298 function = "enet";
306 function = "enet";
315 function = "enet";
323 function = "enet";
/Linux-v5.15/Documentation/devicetree/bindings/soc/fsl/cpm_qe/
Dnetwork.txt4 - fsl,cpm1-scc-enet
5 - fsl,cpm2-scc-enet
6 - fsl,cpm1-fec-enet
7 - fsl,cpm2-fcc-enet (third resource is GFEMR)
8 - fsl,qe-enet
13 compatible = "fsl,mpc8272-fcc-enet",
14 "fsl,cpm2-fcc-enet";
/Linux-v5.15/Documentation/devicetree/bindings/net/
Dnixge.txt4 - compatible: Should be "ni,xge-enet-3.00", but can be "ni,xge-enet-2.00" for
26 compatible = "ni,xge-enet-3.00";
51 compatible = "ni,xge-enet-2.00";
67 compatible = "ni,xge-enet-2.00";
Dezchip_enet.txt4 - compatible: Should be "ezchip,nps-mgt-enet"
6 - interrupts: Should contain the ENET interrupt
11 compatible = "ezchip,nps-mgt-enet";
Dbrcm,bcm4908-enet.yaml4 $id: http://devicetree.org/schemas/net/brcm,bcm4908-enet.yaml#
19 const: brcm,bcm4908-enet
49 compatible = "brcm,bcm4908-enet";
/Linux-v5.15/drivers/net/ethernet/ezchip/
Dnps_enet.h154 * struct nps_enet_priv - Storage of ENET's private information.
155 * @regs_base: Base address of ENET memory-mapped control registers.
170 * nps_enet_reg_set - Sets ENET register with provided value.
171 * @priv: Pointer to EZchip ENET private data structure.
182 * nps_enet_reg_get - Gets value of specified ENET register.
183 * @priv: Pointer to EZchip ENET private data structure.
/Linux-v5.15/drivers/net/ethernet/apm/xgene-v2/
DMakefile6 xgene-enet-v2-objs := main.o mac.o enet.o ring.o mdio.o ethtool.o
7 obj-$(CONFIG_NET_XGENE_V2) += xgene-enet-v2.o
/Linux-v5.15/drivers/pinctrl/
Dpinctrl-lpc18xx.c142 [FUNC_ENET] = "enet",
238 LPC_P(0,0, GPIO, SSP1, ENET, SGPIO, R, R, I2S0_TX_WS,I2S1, 0, ND);
239 LPC_P(0,1, GPIO, SSP1,ENET_ALT,SGPIO, R, R, ENET, I2S1, 0, ND);
255 LPC_P(1,15, GPIO, UART2, SGPIO, ENET, TIMER0, R, R, R, 0, ND);
256 LPC_P(1,16, GPIO, UART2, SGPIO,ENET_ALT,TIMER0, R, R, ENET, 0, ND);
257 LPC_P(1,17, GPIO, UART2, R, ENET, TIMER0, CAN1, SGPIO, R, 0, HD);
258 LPC_P(1,18, GPIO, UART2, R, ENET, TIMER0, CAN1, SGPIO, R, 0, ND);
259 LPC_P(1,19, ENET, SSP1, R, R, CLKOUT, R, I2S0_RX_MCLK,I2S1, 0, ND);
260 LPC_P(1,20, GPIO, SSP1, R, ENET, TIMER0, R, SGPIO, R, 0, ND);
261 LPC_P(2,0, SGPIO, UART0, EMC, USB0, GPIO, R, TIMER3, ENET, 0, ND);
[all …]
/Linux-v5.15/drivers/net/ethernet/stmicro/stmmac/
Ddwmac-socfpga.c282 /* Assert reset to the enet controller before changing the phy mode */ in socfpga_gen5_set_phy_mode()
310 * the enet controller, and operation to start in requested mode in socfpga_gen5_set_phy_mode()
342 /* Assert reset to the enet controller before changing the phy mode */ in socfpga_gen10_set_phy_mode()
367 * the enet controller, and operation to start in requested mode in socfpga_gen10_set_phy_mode()
466 /* Before the enet controller is suspended, the phy is suspended. in socfpga_dwmac_resume()
467 * This causes the phy clock to be gated. The enet controller is in socfpga_dwmac_resume()
469 * the enet controller is resumed. This code makes sure the phy in socfpga_dwmac_resume()
470 * is "resumed" before reinitializing the enet controller since in socfpga_dwmac_resume()
471 * the enet controller depends on an active phy clock to complete in socfpga_dwmac_resume()
473 * with no phy clock input on the Synopsys enet controller. in socfpga_dwmac_resume()
/Linux-v5.15/arch/powerpc/boot/dts/
Dmpc885ads.dts98 compatible = "fsl,mpc885-fec-enet",
99 "fsl,pq1-fec-enet";
110 compatible = "fsl,mpc885-fec-enet",
111 "fsl,pq1-fec-enet";
201 compatible = "fsl,mpc885-scc-enet",
202 "fsl,cpm1-scc-enet";
Dadder875-uboot.dts94 compatible = "fsl,mpc875-fec-enet",
95 "fsl,pq1-fec-enet";
106 compatible = "fsl,mpc875-fec-enet",
107 "fsl,pq1-fec-enet";
Dadder875-redboot.dts95 compatible = "fsl,mpc875-fec-enet",
96 "fsl,pq1-fec-enet";
107 compatible = "fsl,mpc875-fec-enet",
108 "fsl,pq1-fec-enet";
Dep8248e.dts156 compatible = "fsl,mpc8248-fcc-enet",
157 "fsl,cpm2-fcc-enet";
169 compatible = "fsl,mpc8248-fcc-enet",
170 "fsl,cpm2-fcc-enet";
Dtqm8xx.dts111 compatible = "fsl,mpc866-fec-enet",
112 "fsl,pq1-fec-enet";
181 compatible = "fsl,mpc860-scc-enet",
182 "fsl,cpm1-scc-enet";
/Linux-v5.15/drivers/clk/mxs/
Dclk-imx28.c38 #define ENET (CLKCTRL + 0x0140) macro
87 writel_relaxed(1 << BP_ENET_DIV_TIME, ENET + SET); in clk_misc_init()
102 val = readl_relaxed(ENET); in clk_misc_init()
104 writel_relaxed(val, ENET); in clk_misc_init()
189 clks[ptp_sel] = mxs_clk_mux("ptp_sel", ENET, 19, 1, ptp_sels, ARRAY_SIZE(ptp_sels)); in mx28_clocks_init()
203 clks[ptp] = mxs_clk_div("ptp", "ptp_sel", ENET, 21, 6, 27); in mx28_clocks_init()
224 clks[fec] = mxs_clk_gate("fec", "hbus", ENET, 30); in mx28_clocks_init()
231 clks[enet_out] = clk_register_gate(NULL, "enet_out", "pll2", 0, ENET, 18, 0, &mxs_lock); in mx28_clocks_init()
/Linux-v5.15/arch/mips/bcm63xx/
Dclk.c419 CLKDEV_INIT("bcm63xx_enet.0", "enet", &clk_enet0),
420 CLKDEV_INIT("bcm63xx_enet.1", "enet", &clk_enet1),
448 CLKDEV_INIT("bcm63xx_enet.0", "enet", &clk_enet_misc),
462 CLKDEV_INIT("bcm63xx_enet.0", "enet", &clk_enet_misc),
476 CLKDEV_INIT("bcm63xx_enet.0", "enet", &clk_enet_misc),
477 CLKDEV_INIT("bcm63xx_enet.1", "enet", &clk_enet_misc),
495 CLKDEV_INIT("bcm63xx_enet.0", "enet", &clk_enet0),
496 CLKDEV_INIT("bcm63xx_enet.1", "enet", &clk_enet1),
/Linux-v5.15/arch/sparc/include/asm/
Ddma.h41 #define DMA_RST_ENET DMA_RST_SCSI /* Reset the ENET controller */
55 #define DMA_E_BURSTS 0x000c0000 /* ENET: SBUS r/w burst mask */
56 #define DMA_E_BURST32 0x00040000 /* ENET: SBUS 32 byte r/w burst */
57 #define DMA_E_BURST16 0x00000000 /* ENET: SBUS 16 byte r/w burst */
/Linux-v5.15/drivers/net/ethernet/apm/xgene/
DMakefile6 xgene-enet-objs := xgene_enet_hw.o xgene_enet_sgmac.o xgene_enet_xgmac.o \
9 obj-$(CONFIG_NET_XGENE) += xgene-enet.o
/Linux-v5.15/drivers/net/ethernet/freescale/
Dfec.h304 * ENET with AVB IP can support up to 3 independent tx queues and rx queues.
389 /* ENET interrupt coalescing macro define */
400 /* Controller is ENET-MAC */
414 /* ENET IP errata ERR006358
424 /* ENET IP hw AVB
426 * i.MX6SX ENET IP add Audio Video Bridging (AVB) feature support.
437 * The issue exist at i.MX6SX enet IP.
440 /* ENET Block Guide/ Chapter for the iMX6SX (PELE) address one issue:
477 /* i.MX6SX ENET IP supports multiple queues (3 queues), use this quirk to
478 * represents this ENET IP.
[all …]

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