Searched full:emc_xm2dqspadctrl2 (Results 1 – 7 of 7) sorted by relevance
401 0x0800211c /* EMC_XM2DQSPADCTRL2 */505 0x0800211c /* EMC_XM2DQSPADCTRL2 */609 0x0800211c /* EMC_XM2DQSPADCTRL2 */713 0x0800211c /* EMC_XM2DQSPADCTRL2 */815 0x0800013d /* EMC_XM2DQSPADCTRL2 */918 0x0600013d /* EMC_XM2DQSPADCTRL2 */1026 0x0800211c /* EMC_XM2DQSPADCTRL2 */1130 0x0800211c /* EMC_XM2DQSPADCTRL2 */1234 0x0800211c /* EMC_XM2DQSPADCTRL2 */1338 0x0800211c /* EMC_XM2DQSPADCTRL2 */[all …]
96 0x0800013d /* EMC_XM2DQSPADCTRL2 */200 0x0800013d /* EMC_XM2DQSPADCTRL2 */303 0x0800013d /* EMC_XM2DQSPADCTRL2 */
2728 0x0800211c /* EMC_XM2DQSPADCTRL2 */2830 0x0800211c /* EMC_XM2DQSPADCTRL2 */2932 0x0800211c /* EMC_XM2DQSPADCTRL2 */3034 0x0800211c /* EMC_XM2DQSPADCTRL2 */3134 0x0800013d /* EMC_XM2DQSPADCTRL2 */3235 0x0600013d /* EMC_XM2DQSPADCTRL2 */3341 0x0800211c /* EMC_XM2DQSPADCTRL2 */3443 0x0800211c /* EMC_XM2DQSPADCTRL2 */3545 0x0800211c /* EMC_XM2DQSPADCTRL2 */3647 0x0800211c /* EMC_XM2DQSPADCTRL2 */[all …]
160 #define EMC_XM2DQSPADCTRL2 0x2fc macro465 u32 emc_xm2dqspadctrl2; member662 val = readl(emc->regs + EMC_XM2DQSPADCTRL2); in tegra_emc_prepare_timing_change()663 if (timing->emc_xm2dqspadctrl2 & EMC_XM2DQSPADCTRL2_VREF_ENABLE && in tegra_emc_prepare_timing_change()669 if (timing->emc_xm2dqspadctrl2 & EMC_XM2DQSPADCTRL2_RX_FT_REC_ENABLE && in tegra_emc_prepare_timing_change()676 writel(val, emc->regs + EMC_XM2DQSPADCTRL2); in tegra_emc_prepare_timing_change()700 writel(timing->emc_xm2dqspadctrl2, emc->regs + EMC_XM2DQSPADCTRL2); in tegra_emc_prepare_timing_change()969 EMC_READ_PROP(emc_xm2dqspadctrl2, "nvidia,emc-xm2dqspadctrl2") in load_one_timing_from_dt()
108 #define EMC_XM2DQSPADCTRL2 0x2fc macro310 [71] = EMC_XM2DQSPADCTRL2,465 val = readl_relaxed(emc->regs + EMC_XM2DQSPADCTRL2); in emc_dqs_preset()469 writel_relaxed(val, emc->regs + EMC_XM2DQSPADCTRL2); in emc_dqs_preset()
189 - description: EMC_XM2DQSPADCTRL2334 0x0800013d /* EMC_XM2DQSPADCTRL2 */
148 value of the EMC_XM2DQSPADCTRL2 register for this set of timings
