| /Linux-v6.6/drivers/pwm/ |
| D | pwm-ntxec.c | 16 * - The period and duty cycle can't be changed together in one atomic action.
45 * The time base used in the EC is 8MHz, or 125ns. Period and duty cycle are
58 int period, int duty) in ntxec_pwm_set_raw_period_and_duty_cycle() argument
63 * Changes to the period and duty cycle take effect as soon as the in ntxec_pwm_set_raw_period_and_duty_cycle()
66 * duty cycle is fully written. If, in such a case, the old duty cycle in ntxec_pwm_set_raw_period_and_duty_cycle()
69 * To minimize the time between the changes to period and duty cycle in ntxec_pwm_set_raw_period_and_duty_cycle()
75 { NTXEC_REG_DUTY_HIGH, ntxec_reg8(duty >> 8) }, in ntxec_pwm_set_raw_period_and_duty_cycle()
77 { NTXEC_REG_DUTY_LOW, ntxec_reg8(duty) }, in ntxec_pwm_set_raw_period_and_duty_cycle()
87 unsigned int period, duty; in ntxec_pwm_apply() local
94 duty = min_t(u64, state->duty_cycle, period); in ntxec_pwm_apply()
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| D | pwm-sunplus.c | 17 * - In .apply() PWM output need to write register FREQ and DUTY. When first write FREQ
18 * done and not yet write DUTY, it has short timing gap use new FREQ and old DUTY.
60 u32 dd_freq, duty, mode0, mode1; in sunplus_pwm_apply() local
103 /* cal and set pwm duty */ in sunplus_pwm_apply()
111 duty = SP7021_PWM_DUTY_DD_SEL(pwm->hwpwm) | SP7021_PWM_DUTY_MAX; in sunplus_pwm_apply()
117 duty = mul_u64_u64_div_u64(state->duty_cycle, clk_rate, in sunplus_pwm_apply()
119 duty = SP7021_PWM_DUTY_DD_SEL(pwm->hwpwm) | duty; in sunplus_pwm_apply()
121 writel(duty, priv->base + SP7021_PWM_DUTY(pwm->hwpwm)); in sunplus_pwm_apply()
132 u32 mode0, dd_freq, duty; in sunplus_pwm_get_state() local
140 duty = readl(priv->base + SP7021_PWM_DUTY(pwm->hwpwm)); in sunplus_pwm_get_state()
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| D | pwm-renesas-tpu.c | 78 u16 duty; member
179 tpu_pwm_write(tpd, TPU_TGRAn, tpd->duty); in tpu_pwm_timer_start()
183 tpd->channel, tpd->duty, tpd->period); in tpu_pwm_timer_start()
227 tpd->duty = 0; in tpu_pwm_request()
253 u32 duty; in tpu_pwm_config() local
305 duty = mul_u64_u64_div_u64(clk_rate, duty_ns, in tpu_pwm_config()
308 duty = 0; in tpu_pwm_config()
311 "rate %u, prescaler %u, period %u, duty %u\n", in tpu_pwm_config()
312 clk_rate, 1 << (2 * prescaler), (u32)period, duty); in tpu_pwm_config()
319 tpd->duty = duty; in tpu_pwm_config()
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| D | pwm-sprd.c | 75 u32 val, duty, prescale; in sprd_pwm_get_state() local
99 * The duty cycle length is (PRESCALE + 1) * DUTY counter steps. in sprd_pwm_get_state()
102 * duty_ns = NSEC_PER_SEC * (prescale + 1) * duty / clk_rate in sprd_pwm_get_state()
110 duty = val & SPRD_PWM_DUTY_MSK; in sprd_pwm_get_state()
111 tmp = (prescale + 1) * NSEC_PER_SEC * duty; in sprd_pwm_get_state()
126 u32 prescale, duty; in sprd_pwm_config() local
132 * The duty cycle length is (PRESCALE + 1) * DUTY counter steps. in sprd_pwm_config()
139 duty = duty_ns * SPRD_PWM_MOD_MAX / period_ns; in sprd_pwm_config()
148 * Note: Writing DUTY triggers the hardware to actually apply the in sprd_pwm_config()
149 * values written to MOD and DUTY to the output, so must keep writing in sprd_pwm_config()
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| D | pwm-atmel-tcb.c | 37 unsigned duty; /* PWM duty expressed in clk cycles */ member
81 tcbpwm->duty = 0; in atmel_tcb_pwm_request()
95 &tcbpwm->duty); in atmel_tcb_pwm_request()
99 &tcbpwm->duty); in atmel_tcb_pwm_request()
131 * If duty is 0 the timer will be stopped and we have to in atmel_tcb_pwm_disable()
138 if (tcbpwm->duty == 0) in atmel_tcb_pwm_disable()
188 * If duty is 0 the timer will be stopped and we have to in atmel_tcb_pwm_enable()
195 if (tcbpwm->duty == 0) in atmel_tcb_pwm_enable()
221 * If duty is 0 or equal to period there's no need to register in atmel_tcb_pwm_enable()
226 if (tcbpwm->duty != tcbpwm->period && tcbpwm->duty > 0) { in atmel_tcb_pwm_enable()
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| D | pwm-jz4740.c | 104 * Set duty > period. This trick allows the TCU channels in TCU2 mode to in jz4740_pwm_disable()
127 unsigned long period, duty; in jz4740_pwm_apply() local
159 /* Calculate duty value */ in jz4740_pwm_apply()
162 duty = tmp; in jz4740_pwm_apply()
164 if (duty >= period) in jz4740_pwm_apply()
165 duty = period - 1; in jz4740_pwm_apply()
178 /* Set duty */ in jz4740_pwm_apply()
179 regmap_write(jz4740->map, TCU_REG_TDHRc(pwm->hwpwm), duty); in jz4740_pwm_apply()
192 * duty value, then becomes active until the timer reaches the period in jz4740_pwm_apply()
193 * value. In theory, we should then use (period - duty) as the real duty in jz4740_pwm_apply()
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| D | pwm-cros-ec.c | 35 * @duty_cycle: cached duty cycle
81 u16 duty) in cros_ec_pwm_set_duty() argument
99 params->duty = duty; in cros_ec_pwm_set_duty()
154 return resp->duty; in cros_ec_pwm_get_duty()
173 * EC doesn't separate the concept of duty cycle and enabled, but in cros_ec_pwm_apply()
196 dev_err(chip->dev, "error getting initial duty: %d\n", ret); in cros_ec_pwm_get_state()
205 * Note that "disabled" and "duty cycle == 0" are treated the same. If in cros_ec_pwm_get_state()
206 * the cached duty cycle is not zero, used the cached duty cycle. This in cros_ec_pwm_get_state()
207 * ensures that the configured duty cycle is kept across a disable and in cros_ec_pwm_get_state()
211 * will be 0 and the actual duty cycle read from the EC is used. in cros_ec_pwm_get_state()
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| D | pwm-rockchip.c | 41 unsigned long duty; member
85 tmp = readl_relaxed(pc->base + pc->data->regs.duty); in rockchip_pwm_get_state()
107 unsigned long period, duty; in rockchip_pwm_config() local
114 * Since period and duty cycle registers have a width of 32 in rockchip_pwm_config()
123 duty = DIV_ROUND_CLOSEST_ULL(div, pc->data->prescaler * NSEC_PER_SEC); in rockchip_pwm_config()
126 * Lock the period and duty of previous configuration, then in rockchip_pwm_config()
127 * change the duty and period, that would not be effective. in rockchip_pwm_config()
136 writel(duty, pc->base + pc->data->regs.duty); in rockchip_pwm_config()
148 * the configuration of duty, period and polarity in rockchip_pwm_config()
236 .duty = 0x04,
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| D | pwm-iqs620a.c | 9 * to the duty cycle or enable/disable state.
10 * - Changes to the duty cycle or enable/disable state take effect immediately
12 * - The device cannot generate a 0% duty cycle. For duty cycles below 1 / 256
79 * The duty cycle generated by the device is calculated as follows: in iqs620_pwm_apply()
84 * (inclusive). Therefore the lowest duty cycle the device can generate in iqs620_pwm_apply()
87 * For lower duty cycles (e.g. 0), the PWM output is simply disabled to in iqs620_pwm_apply()
117 * Since the device cannot generate a 0% duty cycle, requests to do so in iqs620_pwm_get_state()
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| D | pwm-pca9685.c | 134 /* Helper function to set the duty cycle ratio to duty/4096 (e.g. duty=2048 -> 50%) */
135 static void pca9685_pwm_set_duty(struct pca9685 *pca, int channel, unsigned int duty) in pca9685_pwm_set_duty() argument
140 if (duty == 0) { in pca9685_pwm_set_duty()
144 } else if (duty >= PCA9685_COUNTER_RANGE) { in pca9685_pwm_set_duty()
158 * configured duty cycle / power output. in pca9685_pwm_set_duty()
164 off = (on + duty) % PCA9685_COUNTER_RANGE; in pca9685_pwm_set_duty()
201 /* Read ON register to calculate duty cycle of staggered output */ in pca9685_pwm_get_duty()
367 unsigned long long duty, prescale; in __pca9685_pwm_apply() local
409 duty = PCA9685_COUNTER_RANGE * state->duty_cycle; in __pca9685_pwm_apply()
410 duty = DIV_ROUND_UP_ULL(duty, state->period); in __pca9685_pwm_apply()
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| /Linux-v6.6/drivers/gpu/drm/nouveau/nvkm/subdev/therm/ |
| D | fanpwm.c | 44 u32 divs, duty; in nvkm_fanpwm_get() local
47 ret = therm->func->pwm_get(therm, fan->func.line, &divs, &duty); in nvkm_fanpwm_get()
49 divs = max(divs, duty); in nvkm_fanpwm_get()
51 duty = divs - duty; in nvkm_fanpwm_get()
52 return (duty * 100) / divs; in nvkm_fanpwm_get()
63 u32 divs, duty; in nvkm_fanpwm_set() local
74 duty = ((divs * percent) + 99) / 100; in nvkm_fanpwm_set()
76 duty = divs - duty; in nvkm_fanpwm_set()
78 ret = therm->func->pwm_set(therm, fan->func.line, divs, duty); in nvkm_fanpwm_set()
91 u32 divs, duty; in nvkm_fanpwm_create() local
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| D | fan.c | 39 int duty; in nvkm_fan_update() local
52 /* check that we're not already at the target duty cycle */ in nvkm_fan_update()
53 duty = fan->get(therm); in nvkm_fan_update()
54 if (duty == target) { in nvkm_fan_update()
60 if (!immediate && duty >= 0) { in nvkm_fan_update()
65 if (duty < target) in nvkm_fan_update()
66 duty = min(duty + 3, target); in nvkm_fan_update()
67 else if (duty > target) in nvkm_fan_update()
68 duty = max(duty - 3, target); in nvkm_fan_update()
70 duty = target; in nvkm_fan_update()
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| D | base.c | 44 u16 duty, i; in nvkm_therm_update_trip() local
59 duty = cur_trip->fan_duty; in nvkm_therm_update_trip()
62 duty = 0; in nvkm_therm_update_trip()
66 return duty; in nvkm_therm_update_trip()
74 u16 duty; in nvkm_therm_compute_linear_duty() local
83 duty = (temp - linear_min_temp); in nvkm_therm_compute_linear_duty()
84 duty *= (therm->fan->bios.max_duty - therm->fan->bios.min_duty); in nvkm_therm_compute_linear_duty()
85 duty /= (linear_max_temp - linear_min_temp); in nvkm_therm_compute_linear_duty()
86 duty += therm->fan->bios.min_duty; in nvkm_therm_compute_linear_duty()
87 return duty; in nvkm_therm_compute_linear_duty()
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| /Linux-v6.6/Documentation/devicetree/bindings/regulator/ |
| D | pwm-regulator.yaml | 19 duty-cycle values must be provided via DT. Limitations are that the
21 Intermediary duty-cycle values which would normally allow finer grained
29 appropriate duty-cycle values. This allows for a much more fine grained
31 make an assumption that a %50 duty-cycle value will cause the regulator
49 description: Voltage and Duty-Cycle table.
54 - description: duty-cycle in percent (%)
63 Integer value encoding the duty cycle unit. If not
75 Duty cycle values are expressed in pwm-dutycycle-unit.
104 * Inverted PWM logic, and the duty cycle range is limited
119 /* Voltage Duty-Cycle */
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| /Linux-v6.6/Documentation/hwmon/ |
| D | dme1737.rst | 166 attribute that needs to be set to the maximum attainable RPM (fan at 100% duty-
178 manual mode, the fan speed is set by writing the duty-cycle value to the
180 current duty-cycle as set by the fan controller in the chip. All PWM outputs
191 duty-cycles: full, low, and min. Full is internally hard-wired to 255 (100%)
198 pwm[1-3]_auto_point2_pwm full-speed duty-cycle (255, i.e., 100%)
199 pwm[1-3]_auto_point1_pwm low-speed duty-cycle
200 pwm[1-3]_auto_pwm_min min-speed duty-cycle
208 The chip adjusts the output duty-cycle linearly in the range of auto_point1_pwm
211 auto_point1_temp_hyst value, the output duty-cycle is set to the auto_pwm_min
214 duty-cycle. If any of the temperatures rise above the auto_point3_temp value,
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| D | vt1211.rst | 181 Each PWM has 4 associated distinct output duty-cycles: full, high, low and
186 thermal thresholds exist that controls both PWMs output duty-cycles. The
194 PWM Auto Point PWM Output Duty-Cycle
196 pwm[1-2]_auto_point4_pwm full speed duty-cycle (hard-wired to 255)
197 pwm[1-2]_auto_point3_pwm high speed duty-cycle
198 pwm[1-2]_auto_point2_pwm low speed duty-cycle
199 pwm[1-2]_auto_point1_pwm off duty-cycle (hard-wired to 0)
212 PWM output duty-cycle based on the input temperature:
215 Thermal Threshold Output Duty-Cycle Output Duty-Cycle
218 - full speed duty-cycle full speed duty-cycle
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| D | lm93.rst | 109 a minimum pulse width of 5 clocks (at 22.5kHz => 6.25% duty cycle), and
110 a maximum pulse width of 80 clocks (at 22.5kHz => 99.88% duty cycle).
115 contains a value controlling the duty cycle for the PWM signal used when
117 indicating minimum duty cycle and 15 indicating maximum.
148 and pwm2 are used to set the manual duty cycle; each is an integer (0-255)
149 where 0 is 0% duty cycle, and 255 is 100%. Note that the duty cycle values
152 PWM mode is disabled, the value of pwm1 and pwm2 indicates the current duty
238 A spin-up cycle occurs when a PWM output is commanded from 0% duty cycle to
239 some value > 0%. The LM93 supports a minimum duty cycle during spin-up. These
241 file has the same representation as other PWM duty cycle values. The
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| /Linux-v6.6/Documentation/devicetree/bindings/input/ |
| D | pwm-vibrator.yaml | 14 strength increases based on the duty cycle of the enable PWM channel
15 (100% duty cycle meaning strongest vibration, 0% meaning no vibration).
18 driven at fixed duty cycle. If available this is can be used to increase
39 direction-duty-cycle-ns:
41 Duty cycle of the direction PWM channel in nanoseconds,
58 direction-duty-cycle-ns = <1000000000>;
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| /Linux-v6.6/drivers/clk/meson/ |
| D | sclk-div.c | 12 * The duty cycle may also be set for the LR clock variant. The duty cycle
126 struct clk_duty *duty) in sclk_div_set_duty_cycle() argument
132 memcpy(&sclk->cached_duty, duty, sizeof(*duty)); in sclk_div_set_duty_cycle()
140 struct clk_duty *duty) in sclk_div_get_duty_cycle() argument
147 duty->num = 1; in sclk_div_get_duty_cycle()
148 duty->den = 2; in sclk_div_get_duty_cycle()
153 duty->num = hi + 1; in sclk_div_get_duty_cycle()
154 duty->den = sclk->cached_div; in sclk_div_get_duty_cycle()
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| /Linux-v6.6/drivers/leds/rgb/ |
| D | leds-pwm-multicolor.c | 36 unsigned long long duty; in led_pwm_mc_set() local
45 duty = priv->leds[i].state.period; in led_pwm_mc_set()
46 duty *= mc_cdev->subled_info[i].brightness; in led_pwm_mc_set()
47 do_div(duty, cdev->max_brightness); in led_pwm_mc_set()
50 duty = priv->leds[i].state.period - duty; in led_pwm_mc_set()
52 priv->leds[i].state.duty_cycle = duty; in led_pwm_mc_set()
53 priv->leds[i].state.enabled = duty > 0; in led_pwm_mc_set()
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| /Linux-v6.6/include/linux/ |
| D | pwm.h | 13 * @PWM_POLARITY_NORMAL: a high signal for the duration of the duty-
16 * @PWM_POLARITY_INVERSED: a low signal for the duration of the duty-
51 * @duty_cycle: PWM duty cycle (in nanoseconds)
132 static inline void pwm_set_duty_cycle(struct pwm_device *pwm, unsigned int duty) in pwm_set_duty_cycle() argument
135 pwm->state.duty_cycle = duty; in pwm_set_duty_cycle()
197 * pwm_get_relative_duty_cycle() - Get a relative duty cycle value
198 * @state: PWM state to extract the duty cycle from
199 * @scale: target scale of the relative duty cycle
201 * This functions converts the absolute duty cycle stored in @state (expressed
207 * duty = pwm_get_relative_duty_cycle(&state, 100);
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| /Linux-v6.6/include/trace/events/ |
| D | clk.h | 233 TP_PROTO(struct clk_core *core, struct clk_duty *duty),
235 TP_ARGS(core, duty),
245 __entry->num = duty->num;
246 __entry->den = duty->den;
255 TP_PROTO(struct clk_core *core, struct clk_duty *duty),
257 TP_ARGS(core, duty)
262 TP_PROTO(struct clk_core *core, struct clk_duty *duty),
264 TP_ARGS(core, duty)
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| /Linux-v6.6/drivers/leds/ |
| D | leds-pwm.c | 47 unsigned long long duty = led_dat->pwmstate.period; in led_pwm_set() local
49 duty *= brightness; in led_pwm_set()
50 do_div(duty, max); in led_pwm_set()
53 duty = led_dat->pwmstate.period - duty; in led_pwm_set()
55 led_dat->pwmstate.duty_cycle = duty; in led_pwm_set()
56 led_dat->pwmstate.enabled = duty > 0; in led_pwm_set()
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| /Linux-v6.6/drivers/gpu/drm/nouveau/ |
| D | nouveau_led.c | 42 u32 div, duty; in nouveau_led_get_brightness() local
45 duty = nvif_rd32(device, 0x61c884) & 0x00ffffff; in nouveau_led_get_brightness()
48 return duty * LED_FULL / div; in nouveau_led_get_brightness()
62 u32 div, duty; in nouveau_led_set_brightness() local
65 duty = value * div / LED_FULL; in nouveau_led_set_brightness()
73 nvif_wr32(device, 0x61c884, 0xc0000000 | duty); in nouveau_led_set_brightness()
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| /Linux-v6.6/drivers/gpu/drm/nouveau/nvkm/subdev/volt/ |
| D | gk104.c | 43 u32 div, duty; in gk104_volt_get() local
46 duty = nvkm_rd32(device, 0x20344); in gk104_volt_get()
48 return bios->base + bios->pwm_range * duty / div; in gk104_volt_get()
56 u32 div, duty; in gk104_volt_set() local
60 duty = DIV_ROUND_UP((uv - bios->base) * div, bios->pwm_range); in gk104_volt_set()
63 nvkm_wr32(device, 0x20344, 0x80000000 | duty); in gk104_volt_set()
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