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/Linux-v6.6/drivers/gpu/drm/i915/
DMakefile83 display/intel_display_debugfs.o \
84 display/intel_pipe_crc.o
230 display/hsw_ips.o \
231 display/intel_atomic.o \
232 display/intel_atomic_plane.o \
233 display/intel_audio.o \
234 display/intel_bios.o \
235 display/intel_bw.o \
236 display/intel_cdclk.o \
237 display/intel_color.o \
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/Linux-v6.6/Documentation/devicetree/bindings/display/
Dallwinner,sun4i-a10-display-engine.yaml4 $id: http://devicetree.org/schemas/display/allwinner,sun4i-a10-display-engine.yaml#
7 title: Allwinner A10 Display Engine Pipeline
14 The display engine pipeline (and its entry point, since it can be
18 The Allwinner A10 Display pipeline is composed of several components
22 display pipeline, when there are multiple components of the same
52 - allwinner,sun4i-a10-display-engine
53 - allwinner,sun5i-a10s-display-engine
54 - allwinner,sun5i-a13-display-engine
55 - allwinner,sun6i-a31-display-engine
56 - allwinner,sun6i-a31s-display-engine
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Dallwinner,sun4i-a10-display-frontend.yaml4 $id: http://devicetree.org/schemas/display/allwinner,sun4i-a10-display-frontend.yaml#
7 title: Allwinner A10 Display Engine Frontend
14 The display engine frontend does formats conversion, scaling,
20 - allwinner,sun4i-a10-display-frontend
21 - allwinner,sun5i-a13-display-frontend
22 - allwinner,sun6i-a31-display-frontend
23 - allwinner,sun7i-a20-display-frontend
24 - allwinner,sun8i-a23-display-frontend
25 - allwinner,sun8i-a33-display-frontend
26 - allwinner,sun9i-a80-display-frontend
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Dxylon,logicvc-display.yaml5 $id: http://devicetree.org/schemas/display/xylon,logicvc-display.yaml#
8 title: Xylon LogiCVC display controller
14 The Xylon LogiCVC is a display controller that supports multiple layers.
32 - xylon,logicvc-3.02.a-display
33 - xylon,logicvc-4.01.a-display
67 xylon,display-interface:
79 description: Display output interface (C_DISPLAY_INTERFACE).
81 xylon,display-colorspace:
89 description: Display output colorspace (C_DISPLAY_COLOR_SPACE).
91 xylon,display-depth:
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Dallwinner,sun4i-a10-display-backend.yaml4 $id: http://devicetree.org/schemas/display/allwinner,sun4i-a10-display-backend.yaml#
7 title: Allwinner A10 Display Engine Backend
14 The display engine backend exposes layers and sprites to the system.
19 - allwinner,sun4i-a10-display-backend
20 - allwinner,sun5i-a13-display-backend
21 - allwinner,sun6i-a31-display-backend
22 - allwinner,sun7i-a20-display-backend
23 - allwinner,sun8i-a23-display-backend
24 - allwinner,sun8i-a33-display-backend
25 - allwinner,sun9i-a80-display-backend
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Dsimple-framebuffer.yaml4 $id: http://devicetree.org/schemas/display/simple-framebuffer.yaml#
14 the bootloader, with the assumption that the display hardware has
22 If the devicetree contains nodes for the display hardware used by a
24 display, which contains a phandle pointing to the primary display
30 physical width and height of the display. If no panel node is given,
34 It is advised to add display# aliases to help the OS determine how
35 to number things. If display# aliases are used, then if the simplefb
36 node contains a display property then the /aliases/display# path
37 must point to the display hw node the display property points to,
42 to it, or to the primary display hw node, as with display#
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Dcirrus,clps711x-fb.txt8 - display : phandle to a display node as described in
9 Documentation/devicetree/bindings/display/panel/display-timing.txt.
10 Additionally, the display node has to define properties:
25 display = <&display>;
28 display: display {
33 display-timings {
/Linux-v6.6/Documentation/gpu/amdgpu/display/
Ddc-glossary.rst5 On this page, we try to keep track of acronyms related to the display
37 * DISPCLK: Display Clock
39 * DCFCLK: Display Controller Fabric Clock
56 Display Abstraction layer
59 Display Core
62 Display Controller
68 Display Controller Engine
71 Display Controller HUB
80 Display Core Next
83 Display Clock Generator block
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Dindex.rst1 .. _amdgpu-display-core:
4 drm/amd/display - Display Core (DC)
7 AMD display engine is partially shared with other operating systems; for this
8 reason, our Display Core Driver is divided into two pieces:
10 1. **Display Core (DC)** contains the OS-agnostic components. Things like
12 2. **Display Manager (DM)** contains the OS-dependent components. Hooks to the
15 The display pipe is responsible for "scanning out" a rendered frame from the
16 GPU memory (also called VRAM, FrameBuffer, etc.) to a display. In other words,
28 display-manager.rst
/Linux-v6.6/drivers/media/platform/renesas/vsp1/
Dvsp1_dl.c3 * vsp1_dl.c -- R-Car VSP1 Display List
41 * struct vsp1_dl_ext_header - Extended display list header
45 * @pre_ext_dl_plist: start address of pre-extended display list bodies
47 * @post_ext_dl_plist: start address of post-extended display list bodies
79 * struct vsp1_pre_ext_dl_body - Pre Extended Display List Body
80 * @opcode: Extended display list command operation code
93 * struct vsp1_dl_body - Display list body
94 * @list: entry in the display list list of bodies
121 * struct vsp1_dl_body_pool - display list body pool
145 * struct vsp1_dl_cmd_pool - Display List commands pool
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/Linux-v6.6/drivers/soc/sunxi/
Dsunxi_mbus.c13 * The display engine virtual devices are not strictly speaking
18 "allwinner,sun4i-a10-display-engine",
19 "allwinner,sun5i-a10s-display-engine",
20 "allwinner,sun5i-a13-display-engine",
21 "allwinner,sun6i-a31-display-engine",
22 "allwinner,sun6i-a31s-display-engine",
23 "allwinner,sun7i-a20-display-engine",
24 "allwinner,sun8i-a23-display-engine",
25 "allwinner,sun8i-a33-display-engine",
26 "allwinner,sun9i-a80-display-engine",
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/Linux-v6.6/drivers/gpu/drm/i915/display/
Dintel_hotplug.c35 * Simply put, hotplug occurs when a display is connected to or disconnected
37 * Display Port short pulses and MST devices involved, complicating matters.
48 * further processing to appropriate bottom halves (Display Port specific and
51 * The Display Port work function i915_digport_work_func() calls into
71 * seen when display port sink is connected, hence on platforms whose DP
74 * this is specific to DP sinks handled by this routine and any other display
126 * stored in @dev_priv->display.hotplug.hpd_storm_threshold which defaults to
132 * &dev_priv->display.hotplug.hpd_storm_threshold. However, some older systems also
147 struct intel_hotplug *hpd = &dev_priv->display.hotplug; in intel_hpd_irq_storm_detect()
155 (!long_hpd && !dev_priv->display.hotplug.hpd_short_storm_enabled)) in intel_hpd_irq_storm_detect()
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Dintel_wm.c47 if (i915->display.funcs.wm->update_wm) in intel_update_watermarks()
48 i915->display.funcs.wm->update_wm(i915); in intel_update_watermarks()
56 if (i915->display.funcs.wm->compute_pipe_wm) in intel_compute_pipe_wm()
57 return i915->display.funcs.wm->compute_pipe_wm(state, crtc); in intel_compute_pipe_wm()
67 if (!i915->display.funcs.wm->compute_intermediate_wm) in intel_compute_intermediate_wm()
70 if (drm_WARN_ON(&i915->drm, !i915->display.funcs.wm->compute_pipe_wm)) in intel_compute_intermediate_wm()
73 return i915->display.funcs.wm->compute_intermediate_wm(state, crtc); in intel_compute_intermediate_wm()
81 if (i915->display.funcs.wm->initial_watermarks) { in intel_initial_watermarks()
82 i915->display.funcs.wm->initial_watermarks(state, crtc); in intel_initial_watermarks()
94 if (i915->display.funcs.wm->atomic_update_watermarks) in intel_atomic_update_watermarks()
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Dintel_frontbuffer.c51 * The other type of display power saving feature only cares about busyness
84 spin_lock(&i915->display.fb_tracking.lock); in frontbuffer_flush()
85 frontbuffer_bits &= ~i915->display.fb_tracking.busy_bits; in frontbuffer_flush()
86 spin_unlock(&i915->display.fb_tracking.lock); in frontbuffer_flush()
114 spin_lock(&i915->display.fb_tracking.lock); in intel_frontbuffer_flip_prepare()
115 i915->display.fb_tracking.flip_bits |= frontbuffer_bits; in intel_frontbuffer_flip_prepare()
117 i915->display.fb_tracking.busy_bits &= ~frontbuffer_bits; in intel_frontbuffer_flip_prepare()
118 spin_unlock(&i915->display.fb_tracking.lock); in intel_frontbuffer_flip_prepare()
134 spin_lock(&i915->display.fb_tracking.lock); in intel_frontbuffer_flip_complete()
136 frontbuffer_bits &= i915->display.fb_tracking.flip_bits; in intel_frontbuffer_flip_complete()
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/Linux-v6.6/drivers/video/fbdev/omap2/omapfb/
Domapfb-ioctl.c206 struct omap_dss_device *display = fb2display(fbi); in omapfb_setup_mem() local
216 if (display && display->driver->sync) in omapfb_setup_mem()
217 display->driver->sync(display); in omapfb_setup_mem()
281 struct omap_dss_device *display = fb2display(fbi); in omapfb_update_window() local
284 if (!display) in omapfb_update_window()
290 display->driver->get_resolution(display, &dw, &dh); in omapfb_update_window()
295 return display->driver->update(display, x, y, w, h); in omapfb_update_window()
301 struct omap_dss_device *display = fb2display(fbi); in omapfb_set_update_mode() local
307 if (!display) in omapfb_set_update_mode()
315 d = get_display_data(fbdev, display); in omapfb_set_update_mode()
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/Linux-v6.6/drivers/auxdisplay/
Dline-display.c3 * Character line display core support
20 #include "line-display.h"
25 * linedisp_scroll() - scroll the display by a character
28 * Scroll the current message along the display by one character, rearming the
47 /* update the display */ in linedisp_scroll()
62 * @msg: the message to display
65 * Display a new message @msg on the display. @msg can be longer than the
66 * number of characters the display can display, in which case it will begin
67 * scrolling across the display.
87 /* Clear the display */ in linedisp_display()
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/Linux-v6.6/Documentation/devicetree/bindings/auxdisplay/
Dmodtronix,lcd2s.yaml7 title: Modtronix engineering LCD2S Character LCD Display
13 The LCD2S is a Character LCD Display manufactured by Modtronix Engineering.
14 The display supports a serial I2C and SPI interface. The driver currently
24 I2C bus address of the display.
26 display-height-chars:
27 description: Height of the display, in character cells.
32 display-width-chars:
33 description: Width of the display, in character cells.
41 - display-height-chars
42 - display-width-chars
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/Linux-v6.6/Documentation/devicetree/bindings/display/tegra/
Dnvidia,tegra186-display.yaml4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra186-display.yaml#
7 title: NVIDIA Tegra186 (and later) Display Hub
15 pattern: "^display-hub@[0-9a-f]+$"
19 - nvidia,tegra186-display
20 - nvidia,tegra194-display
44 - description: display hub reset
69 "^display@[0-9a-f]+$":
77 const: nvidia,tegra186-display
82 - description: display core clock
83 - description: display stream compression clock
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/Linux-v6.6/drivers/staging/fbtft/
Dfbtft-core.c251 "%s: start_line=%u is larger than end_line=%u. Shouldn't happen, will do full display update\n", in fbtft_update_display()
259 …"%s: start_line=%u or end_line=%u is larger than max=%d. Shouldn't happen, will do full display up… in fbtft_update_display()
278 "%s: write_vmem failed to update display buffer\n", in fbtft_update_display()
295 "Display update: %ld kB/s, fps=%ld\n", in fbtft_update_display()
312 /* Mark display lines/area as dirty */ in fbtft_mkdirty()
320 /* Schedule deferred_io to update display (no-op if already on queue)*/ in fbtft_mkdirty()
335 /* set display line markers as clean */ in fbtft_deferred_io()
340 /* Mark display lines as dirty */ in fbtft_deferred_io()
517 * @display: pointer to structure describing the display
519 * @pdata: platform data for the display in use
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/Linux-v6.6/drivers/acpi/acpica/
Dutbuffer.c22 * display - BYTE, WORD, DWORD, or QWORD display:
27 * base_offset - Beginning buffer offset (display only)
34 void acpi_ut_dump_buffer(u8 *buffer, u32 count, u32 display, u32 base_offset) in acpi_ut_dump_buffer() argument
40 u32 display_data_only = display & DB_DISPLAY_DATA_ONLY; in acpi_ut_dump_buffer()
42 display &= ~DB_DISPLAY_DATA_ONLY; in acpi_ut_dump_buffer()
49 display = DB_BYTE_DISPLAY; in acpi_ut_dump_buffer()
69 acpi_os_printf("%*s", ((display * 2) + 1), " "); in acpi_ut_dump_buffer()
70 j += display; in acpi_ut_dump_buffer()
74 switch (display) { in acpi_ut_dump_buffer()
76 default: /* Default is BYTE display */ in acpi_ut_dump_buffer()
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/Linux-v6.6/Documentation/devicetree/bindings/display/panel/
Dpanel-simple.yaml4 $id: http://devicetree.org/schemas/display/panel/panel-simple.yaml#
17 The panel may use an OF graph binding for the association to the display,
18 or it may be a direct child node of the display.
118 # DLC Display Co. DLC1010GIG 10.1" WXGA TFT LCD Panel
120 # Emerging Display Technology Corp. 3.5" QVGA TFT LCD panel
122 # Emerging Display Technology Corp. 5.7" VGA TFT LCD panel
125 # Emerging Display Technology Corp. 3.5" WVGA TFT LCD panel with
128 # Emerging Display Technology Corp. 480x272 TFT Display with capacitive touch
130 # Emerging Display Technology Corp. 480x272 TFT Display
132 # Emerging Display Technology Corp. WVGA TFT Display with capacitive touch
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/Linux-v6.6/Documentation/devicetree/bindings/display/sprd/
Dsprd,display-subsystem.yaml4 $id: http://devicetree.org/schemas/display/sprd/sprd,display-subsystem.yaml#
14 DPU devices or other display interface nodes that comprise the
17 Unisoc's display pipeline have several components as below description,
18 multi display controllers and corresponding physical interfaces.
19 For different display scenarios, dpu0 and dpu1 maybe binding to different
23 dpu0 and dpu1 both binding to DSI for dual mipi-dsi display;
24 dpu0 binding to DSI for primary display, and dpu1 binding to DP for external display;
44 const: sprd,display-subsystem
51 Should contain a list of phandles pointing to display interface port
62 display-subsystem {
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/Linux-v6.6/include/video/
Ds1d13xxxfb.h44 #define S1DREG_LCD_DISP_HWIDTH 0x0032 /* LCD Horizontal Display Width Register: ((val)+1)*8)=pix/l…
45 #define S1DREG_LCD_NDISP_HPER 0x0034 /* LCD Horizontal Non-Display Period Register: ((val)+1)*8)=N…
48 #define S1DREG_LCD_DISP_VHEIGHT0 0x0038 /* LCD Vertical Display Height Register 0 */
49 #define S1DREG_LCD_DISP_VHEIGHT1 0x0039 /* LCD Vertical Display Height Register 1 */
50 #define S1DREG_LCD_NDISP_VPER 0x003A /* LCD Vertical Non-Display Period Register: (val)+1=NDlines …
53 #define S1DREG_LCD_DISP_MODE 0x0040 /* LCD Display Mode Register */
55 #define S1DREG_LCD_DISP_START0 0x0042 /* LCD Display Start Address Register 0 */
56 #define S1DREG_LCD_DISP_START1 0x0043 /* LCD Display Start Address Register 1 */
57 #define S1DREG_LCD_DISP_START2 0x0044 /* LCD Display Start Address Register 2 */
61 #define S1DREG_LCD_DISP_FIFO_HTC 0x004A /* LCD Display FIFO High Threshold Control Register */
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/Linux-v6.6/drivers/gpu/drm/amd/display/modules/hdcp/
Dhdcp.c255 struct mod_hdcp_display *display, in update_display_adjustments() argument
262 display->adjust.disable == true && in update_display_adjustments()
264 display->adjust.disable = false; in update_display_adjustments()
271 display->adjust.disable = true; in update_display_adjustments()
275 memcmp(adj, &display->adjust, in update_display_adjustments()
320 struct mod_hdcp_link *link, struct mod_hdcp_display *display, in mod_hdcp_add_display() argument
326 HDCP_TOP_INTERFACE_TRACE_WITH_INDEX(hdcp, display->index); in mod_hdcp_add_display()
329 /* skip inactive display */ in mod_hdcp_add_display()
330 if (display->state != MOD_HDCP_DISPLAY_ACTIVE) { in mod_hdcp_add_display()
335 /* check existing display container */ in mod_hdcp_add_display()
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/Linux-v6.6/Documentation/userspace-api/media/v4l/
Dext-ctrls-colorimetry.rst49 The mastering display defines the color volume (the color primaries,
50 white point and luminance range) of a display considered to be the
51 mastering display for the current video content.
65 primary component c of the mastering display in increments of 0.00002.
66 For describing the mastering display that uses Red, Green and Blue
73 primary component c of the mastering display in increments of 0.00002.
74 For describing the mastering display that uses Red, Green and Blue
81 point of the mastering display in increments of 0.00002.
85 point of the mastering display in increments of 0.00002.
88 - Specifies the nominal maximum display luminance of the mastering
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