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/Linux-v5.10/drivers/usb/dwc3/
Dcore.c45 * @dwc: pointer to our context structure
47 static int dwc3_get_dr_mode(struct dwc3 *dwc) in dwc3_get_dr_mode() argument
50 struct device *dev = dwc->dev; in dwc3_get_dr_mode()
53 if (dwc->dr_mode == USB_DR_MODE_UNKNOWN) in dwc3_get_dr_mode()
54 dwc->dr_mode = USB_DR_MODE_OTG; in dwc3_get_dr_mode()
56 mode = dwc->dr_mode; in dwc3_get_dr_mode()
57 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); in dwc3_get_dr_mode()
89 !device_property_read_bool(dwc->dev, "usb-role-switch")) && in dwc3_get_dr_mode()
94 if (mode != dwc->dr_mode) { in dwc3_get_dr_mode()
99 dwc->dr_mode = mode; in dwc3_get_dr_mode()
[all …]
Ddrd.c19 static void dwc3_otg_disable_events(struct dwc3 *dwc, u32 disable_mask) in dwc3_otg_disable_events() argument
21 u32 reg = dwc3_readl(dwc->regs, DWC3_OEVTEN); in dwc3_otg_disable_events()
24 dwc3_writel(dwc->regs, DWC3_OEVTEN, reg); in dwc3_otg_disable_events()
27 static void dwc3_otg_enable_events(struct dwc3 *dwc, u32 enable_mask) in dwc3_otg_enable_events() argument
29 u32 reg = dwc3_readl(dwc->regs, DWC3_OEVTEN); in dwc3_otg_enable_events()
32 dwc3_writel(dwc->regs, DWC3_OEVTEN, reg); in dwc3_otg_enable_events()
35 static void dwc3_otg_clear_events(struct dwc3 *dwc) in dwc3_otg_clear_events() argument
37 u32 reg = dwc3_readl(dwc->regs, DWC3_OEVT); in dwc3_otg_clear_events()
39 dwc3_writel(dwc->regs, DWC3_OEVTEN, reg); in dwc3_otg_clear_events()
54 struct dwc3 *dwc = _dwc; in dwc3_otg_thread_irq() local
[all …]
Dep0.c30 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep);
31 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
38 struct dwc3 *dwc; in dwc3_ep0_prepare_one_trb() local
40 dwc = dep->dwc; in dwc3_ep0_prepare_one_trb()
41 trb = &dwc->ep0_trb[dep->trb_enqueue]; in dwc3_ep0_prepare_one_trb()
66 struct dwc3 *dwc; in dwc3_ep0_start_trans() local
72 dwc = dep->dwc; in dwc3_ep0_start_trans()
75 params.param0 = upper_32_bits(dwc->ep0_trb_addr); in dwc3_ep0_start_trans()
76 params.param1 = lower_32_bits(dwc->ep0_trb_addr); in dwc3_ep0_start_trans()
82 dwc->ep0_next_event = DWC3_EP0_COMPLETE; in dwc3_ep0_start_trans()
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Dgadget.c35 * @dwc: pointer to our context structure
41 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode) in dwc3_gadget_set_test_mode() argument
45 reg = dwc3_readl(dwc->regs, DWC3_DCTL); in dwc3_gadget_set_test_mode()
60 dwc3_gadget_dctl_write_safe(dwc, reg); in dwc3_gadget_set_test_mode()
67 * @dwc: pointer to our context structure
72 int dwc3_gadget_get_link_state(struct dwc3 *dwc) in dwc3_gadget_get_link_state() argument
76 reg = dwc3_readl(dwc->regs, DWC3_DSTS); in dwc3_gadget_get_link_state()
83 * @dwc: pointer to our context structure
89 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state) in dwc3_gadget_set_link_state() argument
100 reg = dwc3_readl(dwc->regs, DWC3_DSTS); in dwc3_gadget_set_link_state()
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Ddebugfs.c282 struct dwc3 *dwc = s->private; in dwc3_host_lsp() local
288 dbc_enabled = !!(dwc->hwparams.hwparams1 & DWC3_GHWPARAMS1_ENDBC); in dwc3_host_lsp()
290 sel = dwc->dbg_lsp_select; in dwc3_host_lsp()
298 dwc3_writel(dwc->regs, DWC3_GDBGLSPMUX, reg); in dwc3_host_lsp()
299 val = dwc3_readl(dwc->regs, DWC3_GDBGLSP); in dwc3_host_lsp()
304 dwc3_writel(dwc->regs, DWC3_GDBGLSPMUX, reg); in dwc3_host_lsp()
305 val = dwc3_readl(dwc->regs, DWC3_GDBGLSP); in dwc3_host_lsp()
312 struct dwc3 *dwc = s->private; in dwc3_gadget_lsp() local
318 dwc3_writel(dwc->regs, DWC3_GDBGLSPMUX, reg); in dwc3_gadget_lsp()
319 reg = dwc3_readl(dwc->regs, DWC3_GDBGLSP); in dwc3_gadget_lsp()
[all …]
Dulpi.c20 static int dwc3_ulpi_busyloop(struct dwc3 *dwc) in dwc3_ulpi_busyloop() argument
26 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYACC(0)); in dwc3_ulpi_busyloop()
37 struct dwc3 *dwc = dev_get_drvdata(dev); in dwc3_ulpi_read() local
41 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); in dwc3_ulpi_read()
44 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); in dwc3_ulpi_read()
48 dwc3_writel(dwc->regs, DWC3_GUSB2PHYACC(0), reg); in dwc3_ulpi_read()
50 ret = dwc3_ulpi_busyloop(dwc); in dwc3_ulpi_read()
54 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYACC(0)); in dwc3_ulpi_read()
61 struct dwc3 *dwc = dev_get_drvdata(dev); in dwc3_ulpi_write() local
64 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); in dwc3_ulpi_write()
[all …]
Dhost.c15 static int dwc3_host_get_irq(struct dwc3 *dwc) in dwc3_host_get_irq() argument
17 struct platform_device *dwc3_pdev = to_platform_device(dwc->dev); in dwc3_host_get_irq()
45 int dwc3_host_init(struct dwc3 *dwc) in dwc3_host_init() argument
51 struct platform_device *dwc3_pdev = to_platform_device(dwc->dev); in dwc3_host_init()
54 irq = dwc3_host_get_irq(dwc); in dwc3_host_init()
67 dwc->xhci_resources[1].start = irq; in dwc3_host_init()
68 dwc->xhci_resources[1].end = irq; in dwc3_host_init()
69 dwc->xhci_resources[1].flags = res->flags; in dwc3_host_init()
70 dwc->xhci_resources[1].name = res->name; in dwc3_host_init()
74 dev_err(dwc->dev, "couldn't allocate xHCI device\n"); in dwc3_host_init()
[all …]
Ddwc3-pci.c145 static int dwc3_pci_quirks(struct dwc3_pci *dwc) in dwc3_pci_quirks() argument
147 struct pci_dev *pdev = dwc->pci; in dwc3_pci_quirks()
153 guid_parse(PCI_INTEL_BXT_DSM_GUID, &dwc->guid); in dwc3_pci_quirks()
154 dwc->has_dsm_for_pm = true; in dwc3_pci_quirks()
208 struct dwc3_pci *dwc = container_of(work, struct dwc3_pci, wakeup_work); in dwc3_pci_resume_work() local
209 struct platform_device *dwc3 = dwc->dwc3; in dwc3_pci_resume_work()
226 struct dwc3_pci *dwc; in dwc3_pci_probe() local
239 dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL); in dwc3_pci_probe()
240 if (!dwc) in dwc3_pci_probe()
243 dwc->dwc3 = platform_device_alloc("dwc3", PLATFORM_DEVID_AUTO); in dwc3_pci_probe()
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Ddwc3-haps.c39 struct dwc3_haps *dwc; in dwc3_haps_probe() local
52 dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL); in dwc3_haps_probe()
53 if (!dwc) in dwc3_haps_probe()
56 dwc->dwc3 = platform_device_alloc("dwc3", PLATFORM_DEVID_AUTO); in dwc3_haps_probe()
57 if (!dwc->dwc3) in dwc3_haps_probe()
71 ret = platform_device_add_resources(dwc->dwc3, res, ARRAY_SIZE(res)); in dwc3_haps_probe()
77 dwc->pci = pci; in dwc3_haps_probe()
78 dwc->dwc3->dev.parent = dev; in dwc3_haps_probe()
80 ret = platform_device_add_properties(dwc->dwc3, initial_properties); in dwc3_haps_probe()
84 ret = platform_device_add(dwc->dwc3); in dwc3_haps_probe()
[all …]
Dcore.h636 * @dwc: pointer to DWC controller
650 struct dwc3 *dwc; member
672 * @dwc: pointer to DWC controller
698 struct dwc3 *dwc; member
822 * @ctrl: DWC-F
1421 void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode);
1422 void dwc3_set_mode(struct dwc3 *dwc, u32 mode);
1426 (dwc->ip == _ip##_IP)
1429 (DWC3_IP_IS(_ip) && dwc->revision == _ip##_REVISION_##_ver)
1432 (DWC3_IP_IS(_ip) && dwc->revision < _ip##_REVISION_##_ver)
[all …]
Dgadget.h108 void dwc3_ep0_interrupt(struct dwc3 *dwc,
110 void dwc3_ep0_out_start(struct dwc3 *dwc);
116 void dwc3_ep0_send_delayed_status(struct dwc3 *dwc);
135 * @dwc: pointer to our context structure
141 static inline void dwc3_gadget_dctl_write_safe(struct dwc3 *dwc, u32 value) in dwc3_gadget_dctl_write_safe() argument
144 dwc3_writel(dwc->regs, DWC3_DCTL, value); in dwc3_gadget_dctl_write_safe()
/Linux-v5.10/drivers/dma/dw/
Dcore.c51 static struct dw_desc *dwc_first_active(struct dw_dma_chan *dwc) in dwc_first_active() argument
53 return to_dw_desc(dwc->active_list.next); in dwc_first_active()
59 struct dw_dma_chan *dwc = to_dw_dma_chan(tx->chan); in dwc_tx_submit() local
63 spin_lock_irqsave(&dwc->lock, flags); in dwc_tx_submit()
72 list_add_tail(&desc->desc_node, &dwc->queue); in dwc_tx_submit()
73 spin_unlock_irqrestore(&dwc->lock, flags); in dwc_tx_submit()
80 static struct dw_desc *dwc_desc_get(struct dw_dma_chan *dwc) in dwc_desc_get() argument
82 struct dw_dma *dw = to_dw_dma(dwc->chan.device); in dwc_desc_get()
90 dwc->descs_allocated++; in dwc_desc_get()
92 dma_async_tx_descriptor_init(&desc->txd, &dwc->chan); in dwc_desc_get()
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Ddw.c14 static void dw_dma_initialize_chan(struct dw_dma_chan *dwc) in dw_dma_initialize_chan() argument
16 struct dw_dma *dw = to_dw_dma(dwc->chan.device); in dw_dma_initialize_chan()
17 u32 cfghi = is_slave_direction(dwc->direction) ? 0 : DWC_CFGH_FIFO_MODE; in dw_dma_initialize_chan()
18 u32 cfglo = DWC_CFGL_CH_PRIOR(dwc->priority); in dw_dma_initialize_chan()
19 bool hs_polarity = dwc->dws.hs_polarity; in dw_dma_initialize_chan()
21 cfghi |= DWC_CFGH_DST_PER(dwc->dws.dst_id); in dw_dma_initialize_chan()
22 cfghi |= DWC_CFGH_SRC_PER(dwc->dws.src_id); in dw_dma_initialize_chan()
28 channel_writel(dwc, CFG_LO, cfglo); in dw_dma_initialize_chan()
29 channel_writel(dwc, CFG_HI, cfghi); in dw_dma_initialize_chan()
32 static void dw_dma_suspend_chan(struct dw_dma_chan *dwc, bool drain) in dw_dma_suspend_chan() argument
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Didma32.c12 static void idma32_initialize_chan(struct dw_dma_chan *dwc) in idma32_initialize_chan() argument
21 cfghi |= IDMA32C_CFGH_DST_PER(dwc->dws.dst_id & 0xf); in idma32_initialize_chan()
22 cfghi |= IDMA32C_CFGH_SRC_PER(dwc->dws.src_id & 0xf); in idma32_initialize_chan()
25 cfghi |= IDMA32C_CFGH_DST_PER_EXT(dwc->dws.dst_id >> 4 & 0x3); in idma32_initialize_chan()
26 cfghi |= IDMA32C_CFGH_SRC_PER_EXT(dwc->dws.src_id >> 4 & 0x3); in idma32_initialize_chan()
28 channel_writel(dwc, CFG_LO, cfglo); in idma32_initialize_chan()
29 channel_writel(dwc, CFG_HI, cfghi); in idma32_initialize_chan()
32 static void idma32_suspend_chan(struct dw_dma_chan *dwc, bool drain) in idma32_suspend_chan() argument
34 u32 cfglo = channel_readl(dwc, CFG_LO); in idma32_suspend_chan()
39 channel_writel(dwc, CFG_LO, cfglo | DWC_CFGL_CH_SUSP); in idma32_suspend_chan()
[all …]
Dregs.h298 __dwc_regs(struct dw_dma_chan *dwc) in __dwc_regs() argument
300 return dwc->ch_regs; in __dwc_regs()
303 #define channel_readl(dwc, name) \ argument
304 readl(&(__dwc_regs(dwc)->name))
305 #define channel_writel(dwc, name, val) \ argument
306 writel((val), &(__dwc_regs(dwc)->name))
326 void (*initialize_chan)(struct dw_dma_chan *dwc);
327 void (*suspend_chan)(struct dw_dma_chan *dwc, bool drain);
328 void (*resume_chan)(struct dw_dma_chan *dwc, bool drain);
329 u32 (*prepare_ctllo)(struct dw_dma_chan *dwc);
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/Linux-v5.10/drivers/net/ethernet/synopsys/
DMakefile6 obj-$(CONFIG_DWC_XLGMAC) += dwc-xlgmac.o
7 dwc-xlgmac-objs := dwc-xlgmac-net.o dwc-xlgmac-desc.o \
8 dwc-xlgmac-hw.o dwc-xlgmac-common.o \
9 dwc-xlgmac-ethtool.o
11 dwc-xlgmac-$(CONFIG_DWC_XLGMAC_PCI) += dwc-xlgmac-pci.o
DKconfig20 tristate "Synopsys DWC Enterprise Ethernet (XLGMAC) driver support"
26 Ethernet (dwc-xlgmac).
34 This selects the pci bus support for the dwc-xlgmac driver.
/Linux-v5.10/Documentation/devicetree/bindings/net/
Dsnps,dwc-qos-ethernet.txt1 * Synopsys DWC Ethernet QoS IP version 4.10 driver (GMAC)
14 - "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10"
16 - "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10"
18 - "snps,dwc-qos-ethernet-4.10"
20 "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10". It is supported to be
72 - "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10":
78 - "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10":
83 - "snps,dwc-qos-ethernet-4.10" (deprecated):
97 - "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10":
99 - "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10":
[all …]
/Linux-v5.10/drivers/scsi/ufs/
DMakefile3 obj-$(CONFIG_SCSI_UFS_DWC_TC_PCI) += tc-dwc-g210-pci.o ufshcd-dwc.o tc-dwc-g210.o
4 obj-$(CONFIG_SCSI_UFS_DWC_TC_PLATFORM) += tc-dwc-g210-pltfrm.o ufshcd-dwc.o tc-dwc-g210.o
Dtc-dwc-g210-pltfrm.c17 #include "ufshcd-dwc.h"
18 #include "tc-dwc-g210.h"
21 * UFS DWC specific variant operations
24 .name = "tc-dwc-g210-pltfm",
30 .name = "tc-dwc-g210-pltfm",
99 .name = "tc-dwc-g210-pltfm",
107 MODULE_ALIAS("platform:tc-dwc-g210-pltfm");
Dtc-dwc-g210-pci.c11 #include "ufshcd-dwc.h"
12 #include "tc-dwc-g210.h"
52 * struct ufs_hba_dwc_vops - UFS DWC specific variant operations
55 .name = "tc-dwc-g210-pci",
162 .name = "tc-dwc-g210-pci",
/Linux-v5.10/Documentation/devicetree/bindings/display/bridge/
Ddw_hdmi.txt5 TX Encoder (DWC HDMI TX). It doesn't constitue a device tree binding
13 - reg: Memory mapped base address and length of the DWC HDMI TX registers.
19 - interrupts: Reference to the DWC HDMI TX interrupt.
24 - clock-names: The DWC HDMI TX uses the following clocks.
30 - ports: The connectivity of the DWC HDMI TX with the rest of the system is
/Linux-v5.10/Documentation/devicetree/bindings/ufs/
Dtc-dwc-g210-pltfrm.txt11 "snps,dwc-ufshcd-1.40a"
19 Example for a setup using a 1.40a DWC Controller with a 6.00 G210 40-bit TC:
20 dwc-ufs@d0000000 {
22 "snps,dwc-ufshcd-1.40a",
/Linux-v5.10/Documentation/devicetree/bindings/display/imx/
Dhdmi.txt1 Freescale i.MX6 DWC HDMI TX Encoder
7 These DT bindings follow the Synopsys DWC HDMI TX bindings defined in
19 - ports: See dw_hdmi.txt. The DWC HDMI shall have between one and four ports,
28 or the functionally-reduced I2C master contained in the DWC HDMI. When
/Linux-v5.10/Documentation/devicetree/bindings/display/rockchip/
Ddw_hdmi-rockchip.txt1 Rockchip DWC HDMI TX Encoder
7 These DT bindings follow the Synopsys DWC HDMI TX bindings defined in
24 - ports: See dw_hdmi.txt. The DWC HDMI shall have a single port numbered 0
32 or the functionally-reduced I2C master contained in the DWC HDMI. When

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