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/Linux-v5.15/drivers/net/wireless/intel/iwlwifi/pcie/
Dctxt-info.c50 struct iwl_dram_data *dram) in iwl_pcie_ctxt_info_alloc_dma() argument
52 dram->block = iwl_pcie_ctxt_info_dma_alloc_coherent(trans, len, in iwl_pcie_ctxt_info_alloc_dma()
53 &dram->physical); in iwl_pcie_ctxt_info_alloc_dma()
54 if (!dram->block) in iwl_pcie_ctxt_info_alloc_dma()
57 dram->size = len; in iwl_pcie_ctxt_info_alloc_dma()
58 memcpy(dram->block, data, len); in iwl_pcie_ctxt_info_alloc_dma()
65 struct iwl_self_init_dram *dram = &trans->init_dram; in iwl_pcie_ctxt_info_free_paging() local
68 if (!dram->paging) { in iwl_pcie_ctxt_info_free_paging()
69 WARN_ON(dram->paging_cnt); in iwl_pcie_ctxt_info_free_paging()
74 for (i = 0; i < dram->paging_cnt; i++) in iwl_pcie_ctxt_info_free_paging()
[all …]
/Linux-v5.15/Documentation/devicetree/bindings/devfreq/
Drk3399_dmc.txt43 clocks freq is half of DRAM clock), default
60 The controller, pi, PHY and DRAM clock will
74 - rockchip,ddr3_odt_dis_freq : When the DRAM type is DDR3, this parameter defines
77 the ODT on the DRAM side and controller side are
80 - rockchip,ddr3_drv : When the DRAM type is DDR3, this parameter defines
81 the DRAM side driver strength in ohms. Default
84 - rockchip,ddr3_odt : When the DRAM type is DDR3, this parameter defines
85 the DRAM side ODT strength in ohms. Default value
88 - rockchip,phy_ddr3_ca_drv : When the DRAM type is DDR3, this parameter defines
93 - rockchip,phy_ddr3_dq_drv : When the DRAM type is DDR3, this parameter defines
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/Linux-v5.15/tools/perf/pmu-events/arch/x86/sandybridge/
Dmemory.json161 "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.DRAM",
164 …on": "Counts all demand & prefetch code reads that miss the LLC and the data returned from dram.",
173 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.DRAM",
176 …on": "Counts all demand & prefetch data reads that miss the LLC and the data returned from dram.",
185 "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.LLC_MISS.DRAM",
188 …Description": "Counts all prefetch code reads that miss the LLC and the data returned from dram.",
197 "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_MISS.DRAM",
200 …Description": "Counts all prefetch data reads that miss the LLC and the data returned from dram.",
209 "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.LLC_MISS.DRAM",
212 …"BriefDescription": "Counts all prefetch RFOs that miss the LLC and the data returned from dram.",
[all …]
/Linux-v5.15/tools/perf/pmu-events/arch/x86/nehalemep/
Dmemory.json10 "BriefDescription": "Offcore data reads satisfied by any DRAM",
32 "BriefDescription": "Offcore data reads satisfied by the local DRAM",
43 "BriefDescription": "Offcore data reads satisfied by a remote DRAM",
54 "BriefDescription": "Offcore code reads satisfied by any DRAM",
76 "BriefDescription": "Offcore code reads satisfied by the local DRAM",
87 "BriefDescription": "Offcore code reads satisfied by a remote DRAM",
98 "BriefDescription": "Offcore requests satisfied by any DRAM",
120 "BriefDescription": "Offcore requests satisfied by the local DRAM",
131 "BriefDescription": "Offcore requests satisfied by a remote DRAM",
142 "BriefDescription": "Offcore RFO requests satisfied by any DRAM",
[all …]
/Linux-v5.15/tools/perf/pmu-events/arch/x86/nehalemex/
Dmemory.json10 "BriefDescription": "Offcore data reads satisfied by any DRAM",
32 "BriefDescription": "Offcore data reads satisfied by the local DRAM",
43 "BriefDescription": "Offcore data reads satisfied by a remote DRAM",
54 "BriefDescription": "Offcore code reads satisfied by any DRAM",
76 "BriefDescription": "Offcore code reads satisfied by the local DRAM",
87 "BriefDescription": "Offcore code reads satisfied by a remote DRAM",
98 "BriefDescription": "Offcore requests satisfied by any DRAM",
120 "BriefDescription": "Offcore requests satisfied by the local DRAM",
131 "BriefDescription": "Offcore requests satisfied by a remote DRAM",
142 "BriefDescription": "Offcore RFO requests satisfied by any DRAM",
[all …]
/Linux-v5.15/tools/perf/pmu-events/arch/x86/westmereex/
Dmemory.json18 "BriefDescription": "Offcore data reads satisfied by any DRAM",
40 "BriefDescription": "Offcore data reads satisfied by the local DRAM",
51 "BriefDescription": "Offcore data reads satisfied by a remote DRAM",
62 "BriefDescription": "Offcore code reads satisfied by any DRAM",
84 "BriefDescription": "Offcore code reads satisfied by the local DRAM",
95 "BriefDescription": "Offcore code reads satisfied by a remote DRAM",
106 "BriefDescription": "Offcore requests satisfied by any DRAM",
128 "BriefDescription": "Offcore requests satisfied by the local DRAM",
139 "BriefDescription": "Offcore requests satisfied by a remote DRAM",
150 "BriefDescription": "Offcore RFO requests satisfied by any DRAM",
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/Linux-v5.15/tools/perf/pmu-events/arch/x86/amdzen1/
Ddata-fabric.json36 …"PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channe…
44 …"PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channe…
52 …"PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channe…
60 …"PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channe…
68 …"PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channe…
76 …"PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channe…
84 …"PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channe…
92 …"PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channe…
/Linux-v5.15/tools/perf/pmu-events/arch/x86/amdzen2/
Ddata-fabric.json36 …"PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channe…
44 …"PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channe…
52 …"PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channe…
60 …"PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channe…
68 …"PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channe…
76 …"PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channe…
84 …"PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channe…
92 …"PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channe…
/Linux-v5.15/tools/perf/pmu-events/arch/x86/amdzen3/
Ddata-fabric.json36 …"PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channe…
44 …"PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channe…
52 …"PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channe…
60 …"PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channe…
68 …"PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channe…
76 …"PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channe…
84 …"PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channe…
92 …"PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channe…
/Linux-v5.15/tools/perf/pmu-events/arch/x86/westmereep-sp/
Dmemory.json10 "BriefDescription": "Offcore data reads satisfied by any DRAM",
32 "BriefDescription": "Offcore data reads satisfied by the local DRAM",
43 "BriefDescription": "Offcore data reads satisfied by a remote DRAM",
54 "BriefDescription": "Offcore code reads satisfied by any DRAM",
76 "BriefDescription": "Offcore code reads satisfied by the local DRAM",
87 "BriefDescription": "Offcore code reads satisfied by a remote DRAM",
98 "BriefDescription": "Offcore requests satisfied by any DRAM",
120 "BriefDescription": "Offcore requests satisfied by the local DRAM",
131 "BriefDescription": "Offcore requests satisfied by a remote DRAM",
142 "BriefDescription": "Offcore RFO requests satisfied by any DRAM",
[all …]
/Linux-v5.15/tools/perf/pmu-events/arch/x86/skylakex/
Duncore-memory.json30 "BriefDescription": "Cycles where DRAM ranks are in power down (CKE) mode",
68 "BriefDescription": "DRAM Page Activate commands sent due to a write request",
73DRAM Page Activate commands sent on this channel due to a write request to the iMC (Memory Control…
78 "BriefDescription": "All DRAM CAS Commands issued",
83DRAM per memory channel. CAS commands are issued to specify the address to read or write on DRAM,…
88 "BriefDescription": "All DRAM Read CAS Commands issued (does not include underfills)",
93DRAM on a per channel basis. CAS commands are issued to specify the address to read or write on D…
98 "BriefDescription": "DRAM Underfill Read CAS Commands issued",
103DRAM due to a partial write, on a per channel basis. CAS commands are issued to specify the addre…
108 …"BriefDescription": "DRAM CAS (Column Address Strobe) Commands.; DRAM WR_CAS (w/ and w/out auto-pr…
[all …]
/Linux-v5.15/tools/perf/pmu-events/arch/x86/cascadelakex/
Duncore-memory.json30 "BriefDescription": "Cycles where DRAM ranks are in power down (CKE) mode+C37",
134 "BriefDescription": "DRAM Page Activate commands sent due to a write request",
139DRAM Page Activate commands sent on this channel due to a write request to the iMC (Memory Control…
144 "BriefDescription": "All DRAM CAS Commands issued",
149DRAM per memory channel. CAS commands are issued to specify the address to read or write on DRAM,…
154 "BriefDescription": "All DRAM Read CAS Commands issued (does not include underfills)",
159DRAM on a per channel basis. CAS commands are issued to specify the address to read or write on D…
164 "BriefDescription": "DRAM Underfill Read CAS Commands issued",
169DRAM due to a partial write, on a per channel basis. CAS commands are issued to specify the addre…
174 …"BriefDescription": "DRAM CAS (Column Address Strobe) Commands.; DRAM WR_CAS (w/ and w/out auto-pr…
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/Linux-v5.15/drivers/net/wireless/intel/iwlwifi/
Diwl-context-info.h9 /* maximmum number of DRAM map entries supported by FW */
79 * struct iwl_context_info_dram - images DRAM map
80 * each entry in the map represents a DRAM chunk of up to 32 KB
81 * @umac_img: UMAC image DRAM map
82 * @lmac_img: LMAC image DRAM map
83 * @virtual_img: paged image DRAM map
116 * @core_dump_addr: core dump (debug DRAM address) start address
138 * dumping DRAM addresses
157 * @dram: firmware image addresses in DRAM
170 struct iwl_context_info_dram dram; member
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Diwl-fh.h31 * host DRAM powered on (via dummy accesses to DRAM) to maintain low-latency
32 * DRAM access when doing Txing or Rxing. The dummy accesses prevent host
33 * from going into a power-savings mode that would cause higher DRAM latency,
39 * be sufficient to maintain fast DRAM response.
50 * Device has 16 base pointer registers, one for each of 16 host-DRAM-resident
53 * bytes from one another. Each TFD circular buffer in DRAM must be 256-byte
101 * In case of DRAM read address which is not aligned to 128B, the TFH will
102 * enable transfer size which doesn't cross 64B DRAM address boundary.
110 * Tx CMD which will be updated in DRAM.
113 * In case of a DRAM Tx CMD update the TFH will update PN and Key ID
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/Linux-v5.15/drivers/tty/serial/
Dicom.c346 void __iomem *dram_ptr = icom_port->dram; in load_code()
360 /* Zero out DRAM */ in load_code()
377 iram_ptr = (char __iomem *)icom_port->dram + ICOM_IRAM_OFFSET; in load_code()
397 iram_ptr = (char __iomem *) icom_port->dram + ICOM_IRAM_OFFSET; in load_code()
405 writeb(V2_HARDWARE, &(icom_port->dram->misc_flags)); in load_code()
411 &(icom_port->dram->HDLCConfigReg)); in load_code()
412 writeb(0x04, &(icom_port->dram->FlagFillIdleTimer)); /* 0.5 seconds */ in load_code()
413 writeb(0x00, &(icom_port->dram->CmdReg)); in load_code()
414 writeb(0x10, &(icom_port->dram->async_config3)); in load_code()
416 ICOM_ACFG_1STOP_BIT), &(icom_port->dram->async_config2)); in load_code()
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/Linux-v5.15/drivers/edac/
Di3000_edac.c25 /* Intel 3000 register addresses - device 0 function 0 - DRAM Controller */
31 #define I3000_EDEAP 0x70 /* Extended DRAM Error Address Pointer (8b)
36 #define I3000_DEAP 0x58 /* DRAM Error Address Pointer (32b)
68 #define I3000_DERRSYN 0x5c /* DRAM Error Syndrome (8b)
70 * 7:0 DRAM ECC Syndrome
79 * 9 LOCK to non-DRAM Memory Flag (LCKF)
82 * 1 Multi-bit DRAM ECC Error Flag (DMERR)
83 * 0 Single-bit DRAM ECC Error Flag (DSERR)
95 * 9 SERR on LOCK to non-DRAM Memory
97 * 8 SERR on DRAM Refresh Timeout
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Di82975x_edac.c34 /* Intel 82975X register addresses - device 0 function 0 - DRAM Controller */
35 #define I82975X_EAP 0x58 /* Dram Error Address Pointer (32b)
42 #define I82975X_DERRSYN 0x5c /* Dram Error SYNdrome (8b)
44 * 7:0 DRAM ECC Syndrome
47 #define I82975X_DES 0x5d /* Dram ERRor DeSTination (8b)
58 * 9 non-DRAM lock error (ndlock)
61 * 1 ECC UE (multibit DRAM error)
62 * 0 ECC CE (singlebit DRAM error)
76 * 9 non-DRAM lock error (ndlock)
79 * 1 ECC UE (multibit DRAM error)
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Damd64_edac.h56 * is within a range affected by memory hoisting. The DRAM Base
57 * (section 3.4.4.1) and DRAM Limit (section 3.4.4.2) registers
60 * If the DRAM Hole Address Register (DHAR) is enabled and the SysAddr
83 * The memory controller for a given node uses its DRAM CS Base and
84 * DRAM CS Mask registers to map an InputAddr to a csrow. See
169 * Function 2 - DRAM controller
317 * See F1x[1, 0][7C:40] DRAM Base/Limit Registers
339 u32 ecc_ctrl; /* DRAM ECC Control reg */
358 u32 dclr0; /* DRAM Configuration Low DCT0 reg */
359 u32 dclr1; /* DRAM Configuration Low DCT1 reg */
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/Linux-v5.15/drivers/pinctrl/
Dpinctrl-gemini.c132 "DRAM",
152 PINCTRL_PIN(2, "A3 DRAM CK"),
153 PINCTRL_PIN(3, "A4 DRAM CK N"),
154 PINCTRL_PIN(4, "A5 DRAM A5"),
155 PINCTRL_PIN(5, "A6 DRAM CKE"),
156 PINCTRL_PIN(6, "A7 DRAM DQ11"),
157 PINCTRL_PIN(7, "A8 DRAM DQ0"),
158 PINCTRL_PIN(8, "A9 DRAM DQ5"),
159 PINCTRL_PIN(9, "A10 DRAM DQ6"),
160 PINCTRL_PIN(10, "A11 DRAM DRAM VREF"),
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/Linux-v5.15/arch/powerpc/platforms/chrp/
Dgg2.h48 #define GG2_PCI_DRAM_BANK0 0x90 /* Control register for DRAM bank #0 */
49 #define GG2_PCI_DRAM_BANK1 0x94 /* Control register for DRAM bank #1 */
50 #define GG2_PCI_DRAM_BANK2 0x98 /* Control register for DRAM bank #2 */
51 #define GG2_PCI_DRAM_BANK3 0x9c /* Control register for DRAM bank #3 */
52 #define GG2_PCI_DRAM_BANK4 0xa0 /* Control register for DRAM bank #4 */
53 #define GG2_PCI_DRAM_BANK5 0xa4 /* Control register for DRAM bank #5 */
56 #define GG2_PCI_DRAM_CTRL 0xc0 /* DRAM control */
/Linux-v5.15/drivers/usb/host/
Dxhci-mvebu.c24 const struct mbus_dram_target_info *dram) in xhci_mvebu_mbus_config() argument
34 /* Program each DRAM CS in a seperate window */ in xhci_mvebu_mbus_config()
35 for (win = 0; win < dram->num_cs; win++) { in xhci_mvebu_mbus_config()
36 const struct mbus_dram_window *cs = dram->cs + win; in xhci_mvebu_mbus_config()
39 (dram->mbus_dram_target_id << 4) | 1, in xhci_mvebu_mbus_config()
52 const struct mbus_dram_target_info *dram; in xhci_mvebu_mbus_init_quirk() local
66 dram = mv_mbus_dram_info(); in xhci_mvebu_mbus_init_quirk()
67 xhci_mvebu_mbus_config(base, dram); in xhci_mvebu_mbus_init_quirk()
/Linux-v5.15/tools/perf/pmu-events/arch/x86/icelakex/
Duncore-memory.json53 "BriefDescription": "DRAM Precharge commands. : Precharge due to read",
63 "BriefDescription": "DRAM Precharge commands. : Precharge due to write",
73 "BriefDescription": "All DRAM read CAS commands issued (including underfills)",
83 "BriefDescription": "All DRAM write CAS commands issued",
93 "BriefDescription": "All DRAM CAS commands issued",
103 "BriefDescription": "Number of DRAM Refreshes Issued",
113 "BriefDescription": "Number of DRAM Refreshes Issued",
123 "BriefDescription": "Number of DRAM Refreshes Issued",
173 "BriefDescription": "DRAM Precharge commands. : Precharge due to page table",
183 "BriefDescription": "DRAM Clockticks",
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/Linux-v5.15/tools/perf/pmu-events/arch/x86/tremontx/
Duncore-other.json289 "BriefDescription": "Data requested of the CPU : Card reading from DRAM",
297 …"PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes)…
302 "BriefDescription": "Data requested of the CPU : Card reading from DRAM",
310 …"PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes)…
315 "BriefDescription": "Data requested of the CPU : Card reading from DRAM",
323 …"PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes)…
328 "BriefDescription": "Data requested of the CPU : Card reading from DRAM",
336 …"PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes)…
341 "BriefDescription": "Data requested of the CPU : Card writing to DRAM",
349 …"PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) t…
[all …]
/Linux-v5.15/tools/perf/pmu-events/arch/x86/ivybridge/
Dmemory.json170 "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.DRAM",
173 …ion": "Counts all demand & prefetch code reads that miss the LLC and the data returned from dram",
182 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.DRAM",
185 …ion": "Counts all demand & prefetch data reads that miss the LLC and the data returned from dram",
194 "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.DRAM",
197 …ts all data/code/rfo reads (demand & prefetch) that miss the LLC and the data returned from dram",
206 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.DRAM",
209 … "BriefDescription": "Counts demand code reads that miss the LLC and the data returned from dram",
218 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.DRAM",
221 … "BriefDescription": "Counts demand data reads that miss the LLC and the data returned from dram",
/Linux-v5.15/tools/perf/pmu-events/arch/x86/knightslanding/
Dmemory.json40 …"BriefDescription": "Counts any Prefetch requests that accounts for data responses from DRAM Far.",
51 …riefDescription": "Counts any Prefetch requests that accounts for data responses from DRAM Local.",
84 … "BriefDescription": "Counts any Read request that accounts for data responses from DRAM Far.",
95 … "BriefDescription": "Counts any Read request that accounts for data responses from DRAM Local.",
128 …emand code reads and prefetch code read requests that accounts for data responses from DRAM Far.",
139 …and code reads and prefetch code read requests that accounts for data responses from DRAM Local.",
172 …n": "Counts Demand cacheable data write requests that accounts for data responses from DRAM Far.",
183 …: "Counts Demand cacheable data write requests that accounts for data responses from DRAM Local.",
216 …acheable data and L1 prefetch data read requests that accounts for data responses from DRAM Far.",
227 …heable data and L1 prefetch data read requests that accounts for data responses from DRAM Local.",
[all …]

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