/Linux-v6.6/arch/arm/mach-omap2/ |
D | sleep24xx.S | 31 * R0 : DLL ctrl value pre-Sleep 36 * when we get called, but the DLL probably isn't. We will wait a bit more in 37 * case the DPLL isn't quite there yet. The code will wait on DLL for DDR even 48 * The DLL load value is not kept in RETENTION or OFF. It needs to be restored 60 mov r5, #0x2000 @ set delay (DPLL relock + DLL relock) 76 strne r0, [r1] @ rewrite DLLA to force DLL reload 78 strne r0, [r1] @ rewrite DLLB to force DLL reload
|
D | sram242x.S | 45 /* dll lock mode */ 52 orr r10, r10, #0x8 @ make sure DLL on (es2 bit pos) 55 bl i_dll_wait @ wait for dll to lock 57 /* get dll value */ 84 /* ensure the DLL has relocked */ 86 mov r4, #0x800 @ delay DLL relock, min 0x400 L3 clocks 172 cmp r2, #0x1 @ (SDR or DDR) do we need to adjust DLL 173 bne freq_out @ leave if SDR, no DLL function 175 /* With DDR, we need to take care of the DLL for the frequency change */ 180 mov r1, #0x2000 @ wait DLL relock, min 0x400 L3 clocks [all …]
|
D | sram243x.S | 45 /* dll lock mode */ 52 orr r10, r10, #0x8 @ make sure DLL on (es2 bit pos) 55 bl i_dll_wait @ wait for dll to lock 57 /* get dll value */ 84 /* ensure the DLL has relocked */ 86 mov r4, #0x800 @ delay DLL relock, min 0x400 L3 clocks 172 cmp r2, #0x1 @ (SDR or DDR) do we need to adjust DLL 173 bne freq_out @ leave if SDR, no DLL function 175 /* With DDR, we need to take care of the DLL for the frequency change */ 180 mov r1, #0x2000 @ wait DLL relock, min 0x400 L3 clocks [all …]
|
D | sdrc2xxx.c | 30 /* Memory timing, DLL mode flags */ 56 * Check the DLL lock state, and return tue if running in unlock mode. 57 * This is needed to compensate for the shifted DLL value in unlock mode. 131 /* With DDR we need to determine the low frequency DLL value */ in omap2xxx_sdrc_init_params() 148 /* set fast timings with DLL filter disabled */ in omap2xxx_sdrc_init_params() 162 /* 90 degree phase for anything below 133MHz + disable DLL filter */ in omap2xxx_sdrc_init_params()
|
D | sdrc.h | 88 u32 slow_dll_ctrl; /* unlock mode, dll value for slow speed */ 89 u32 fast_dll_ctrl; /* unlock mode, dll value for fast speed */ 109 /* Minimum frequency that the SDRC DLL can lock at */
|
D | sleep34xx.S | 263 /* allow DLL powerdown upon hw idle req */ 270 /* Is dll in lock mode? */ 275 /* wait till dll locks */ 289 /* disable/reenable DLL if not locked */ 294 bic r6, #(1<<3) @ disable dll 297 orr r6, r6, #(1<<3) @ enable dll
|
/Linux-v6.6/include/soc/at91/ |
D | sama7-ddr.h | 16 #define DDR3PHY_PIR_DLLBYP (1 << 17) /* DLL Bypass */ 18 #define DDR3PHY_PIR_DLLLOCK (1 << 2) /* DLL Lock */ 19 #define DDR3PHY_PIR_DLLSRST (1 << 1) /* DLL Soft Rest */ 29 #define DDR3PHY_ACDLLCR (0x14) /* DDR3PHY AC DLL Control Register */ 30 #define DDR3PHY_ACDLLCR_DLLSRST (1 << 30) /* DLL Soft Reset */ 49 #define DDR3PHY_DX0DLLCR (0x1CC) /* DDR3PHY DATX8 DLL Control Register */ 50 #define DDR3PHY_DX1DLLCR (0x20C) /* DDR3PHY DATX8 DLL Control Register */ 51 #define DDR3PHY_DXDLLCR_DLLDIS (1 << 31) /* DLL Disable */
|
D | at91sam9_ddrsdr.h | 43 #define AT91_DDRSDRC_RST_DLL (1 << 7) /* Reset DLL */ 45 #define AT91_DDRSDRC_DIS_DLL (1 << 9) /* Disable DLL [SAM9 Only] */ 103 #define AT91_DDRSDRC_DLL 0x24 /* DLL Information Register */
|
/Linux-v6.6/Documentation/devicetree/bindings/mmc/ |
D | cdns,sdhci.yaml | 34 # PHY DLL input delays: 84 # PHY DLL clock delays: 92 cdns,phy-dll-delay-sdclk: 100 cdns,phy-dll-delay-sdclk-hsmmc: 108 cdns,phy-dll-delay-strobe: 155 cdns,phy-dll-delay-sdclk = <0>;
|
D | fsl-imx-esdhc.yaml | 109 This is used to set the clock delay for DLL(Delay Line) on override mode 112 chapter, DLL (Delay Line) section in RM for details. 144 fsl,strobe-dll-delay-target: 147 Specify the strobe dll control slave delay target.
|
/Linux-v6.6/arch/x86/boot/ |
D | early_serial_console.c | 21 #define DLL 0 /* Divisor Latch Low */ macro 39 outb(divisor & 0xff, port + DLL); in early_serial_init() 104 unsigned char lcr, dll, dlh; in probe_baud() local 109 dll = inb(port + DLL); in probe_baud() 112 quot = (dlh << 8) | dll; in probe_baud()
|
/Linux-v6.6/drivers/phy/intel/ |
D | phy-intel-keembay-emmc.c | 76 dev_err(&phy->dev, "turn off the dll failed: %d\n", ret); in keembay_emmc_phy_power() 131 /* Set the frequency of the DLL operation */ in keembay_emmc_phy_power() 135 dev_err(&phy->dev, "set the frequency of dll failed:%d\n", ret); in keembay_emmc_phy_power() 139 /* Turn on the DLL */ in keembay_emmc_phy_power() 143 dev_err(&phy->dev, "turn on the dll failed: %d\n", ret); in keembay_emmc_phy_power() 148 * We turned on the DLL even though the rate was 0 because we the in keembay_emmc_phy_power() 149 * clock might be turned on later. ...but we can't wait for the DLL in keembay_emmc_phy_power() 160 * After enabling analog DLL circuits docs say that we need 10.2 us if in keembay_emmc_phy_power() 168 * NOTE: There appear to be corner cases where the DLL seems to take in keembay_emmc_phy_power()
|
D | phy-intel-lgm-emmc.c | 110 /* Set the frequency of the DLL operation */ in intel_emmc_phy_power() 114 dev_err(&phy->dev, "set the frequency of dll failed:%d\n", ret); in intel_emmc_phy_power() 118 /* Turn on the DLL */ in intel_emmc_phy_power() 122 dev_err(&phy->dev, "turn on the dll failed: %d\n", ret); in intel_emmc_phy_power() 127 * After enabling analog DLL circuits docs say that we need 10.2 us if in intel_emmc_phy_power() 135 * NOTE: There appear to be corner cases where the DLL seems to take in intel_emmc_phy_power()
|
/Linux-v6.6/arch/powerpc/kernel/ |
D | udbg_16550.c | 98 unsigned int dll, base_bauds; in udbg_uart_setup() local 109 dll = base_bauds / speed; in udbg_uart_setup() 115 udbg_uart_out(UART_DLL, dll & 0xff); in udbg_uart_setup() 116 udbg_uart_out(UART_DLM, dll >> 8); in udbg_uart_setup() 127 unsigned int dll, dlm, divisor, prescaler, speed; in udbg_probe_uart_speed() local 136 dll = udbg_uart_in(UART_DLL); in udbg_probe_uart_speed() 138 divisor = dlm << 8 | dll; in udbg_probe_uart_speed()
|
/Linux-v6.6/drivers/phy/rockchip/ |
D | phy-rockchip-emmc.c | 150 * pretty spot on for the DLL range, so warn if we're too in rockchip_emmc_phy_power() 186 /* Set the frequency of the DLL operation */ in rockchip_emmc_phy_power() 192 /* Turn on the DLL */ in rockchip_emmc_phy_power() 200 * We turned on the DLL even though the rate was 0 because we the in rockchip_emmc_phy_power() 201 * clock might be turned on later. ...but we can't wait for the DLL in rockchip_emmc_phy_power() 212 * After enabling analog DLL circuits docs say that we need 10.2 us if in rockchip_emmc_phy_power() 220 * NOTE: There appear to be corner cases where the DLL seems to take in rockchip_emmc_phy_power()
|
/Linux-v6.6/drivers/mmc/host/ |
D | sdhci-esdhc.h | 89 /* DLL Config 0 Register */ 95 /* DLL Config 1 Register */ 99 /* DLL Status 0 Register */
|
D | sdhci-pci-o2micro.c | 187 * This function is used to detect dll lock status. 188 * Since the dll lock status bit will toggle randomly 238 * This function is used to fix o2 dll shift issue. 281 * need wait at least 5ms for dll status stable, in sdhci_o2_dll_recovery() 291 pr_warn("%s: DLL unlocked when dll_adjust_count is %d.\n", in sdhci_o2_dll_recovery() 304 pr_err("%s: DLL adjust over max times\n", in sdhci_o2_dll_recovery() 361 /* Set pcr 0x354[16] to choose dll clock, and set the default phase */ in sdhci_o2_execute_tuning() 382 /* wait DLL lock, timeout value 5ms */ in sdhci_o2_execute_tuning() 385 pr_warn("%s: DLL can't lock in 5ms after force L0 during tuning.\n", in sdhci_o2_execute_tuning() 388 * Judge the tuning reason, whether caused by dll shift in sdhci_o2_execute_tuning() [all …]
|
D | sdhci-msm.c | 450 * Write the selected DLL clock output phase (0 ... 15) in msm_config_cm_dll_phase() 474 dev_err(mmc_dev(mmc), "%s: Failed to set DLL phase: %d\n", in msm_config_cm_dll_phase() 483 * DLL clock output phases that can be used as sampling 487 * Select the 3/4 of the range and configure the DLL with the 488 * selected DLL clock output phase. 623 /* Initialize the DLL (Programmable Delay Line) */ 641 * Make sure that clock is always enabled when DLL in msm_init_cm_dll() 703 /* wait for 5us before enabling DLL clock */ in msm_init_cm_dll() 730 * Configure DLL user control register to enable DLL status. in msm_init_cm_dll() 767 dev_err(mmc_dev(mmc), "%s: DLL failed to LOCK\n", in msm_init_cm_dll() [all …]
|
D | sdhci-xenon-phy.c | 125 /* Offset of DLL Control register */ 129 /* DLL Update Enable bit */ 316 * Enable eMMC PHY HW DLL 317 * DLL should be enabled and stable before HS200/SDR104 tuning, 335 /* Enable DLL */ in xenon_emmc_phy_enable_dll() 364 dev_err(mmc_dev(host->mmc), "Wait for DLL Lock time-out\n"); in xenon_emmc_phy_enable_dll() 374 * Enable HW DLL and set the TUNING_STEP 391 /* Achieve TUNING_STEP with HW DLL help */ in xenon_emmc_phy_config_tuning() 461 * 3. DLL is enabled in xenon_emmc_phy_strobe_delay_adj()
|
/Linux-v6.6/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ |
D | gddr3.c | 73 int CL, WR, CWL, DLL = 0, ODT = 0, RON, hi; in nvkm_gddr3_calc() local 80 DLL = !ram->next->bios.ramcfg_DLLoff; in nvkm_gddr3_calc() 89 DLL = !(ram->mr[1] & 0x1); in nvkm_gddr3_calc() 117 ram->mr[1] |= !DLL << 6; in nvkm_gddr3_calc()
|
D | sddr2.c | 63 int CL, WR, DLL = 0, ODT = 0; in nvkm_sddr2_calc() local 69 DLL = !ram->next->bios.ramcfg_DLLoff; in nvkm_sddr2_calc() 98 ram->mr[1] |= !DLL; in nvkm_sddr2_calc()
|
D | sddr3.c | 72 int CWL, CL, WR, DLL = 0, ODT = 0; in nvkm_sddr3_calc() local 74 DLL = !ram->next->bios.ramcfg_DLLoff; in nvkm_sddr3_calc() 115 ram->mr[1] |= !DLL; in nvkm_sddr3_calc()
|
/Linux-v6.6/Documentation/devicetree/bindings/memory-controllers/ |
D | rockchip,rk3399-dmc.yaml | 108 Defines the DDR3 DLL bypass frequency in MHz. When DDR frequency is less 109 than DRAM_DLL_DISB_FREQ, DDR3 DLL will be bypassed. 110 Note: if DLL was bypassed, the odt will also stop working. 116 Defines the PHY dll bypass frequency in MHz (Mega Hz). When DDR frequency 117 is less than DRAM_DLL_DISB_FREQ, PHY DLL will be bypassed. 118 Note: PHY DLL and PHY ODT are independent.
|
/Linux-v6.6/drivers/tty/serial/8250/ |
D | 8250_pxa.c | 65 unsigned int dll; in serial_pxa_dl_write() local 72 dll = serial_in(up, UART_DLL); in serial_pxa_dl_write() 73 WARN_ON(dll != (value & 0xff)); in serial_pxa_dl_write()
|
/Linux-v6.6/drivers/net/ethernet/cavium/thunder/ |
D | thunder_xcv.c | 69 /* Take DLL out of reset */ in xcv_init_hw() 78 /* Wait for DLL to lock */ in xcv_init_hw() 81 /* Configure DLL - enable or bypass in xcv_init_hw()
|