| /Linux-v5.15/drivers/gpu/drm/amd/display/dc/dce112/ |
| D | dce112_resource.c | 39 #include "dce/dce_mem_input.h"
40 #include "dce/dce_transform.h"
41 #include "dce/dce_link_encoder.h"
42 #include "dce/dce_stream_encoder.h"
43 #include "dce/dce_audio.h"
44 #include "dce/dce_opp.h"
45 #include "dce/dce_ipp.h"
46 #include "dce/dce_clock_source.h"
48 #include "dce/dce_hwseq.h"
50 #include "dce/dce_abm.h"
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| /Linux-v5.15/drivers/gpu/drm/amd/display/dc/dce110/ |
| D | dce110_resource.c | 36 #include "dce/dce_audio.h"
40 #include "dce/dce_link_encoder.h"
41 #include "dce/dce_stream_encoder.h"
42 #include "dce/dce_mem_input.h"
44 #include "dce/dce_ipp.h"
45 #include "dce/dce_transform.h"
47 #include "dce/dce_opp.h"
49 #include "dce/dce_clock_source.h"
50 #include "dce/dce_hwseq.h"
52 #include "dce/dce_aux.h"
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| D | dce110_opp_v.c | 29 #include "dce/dce_11_0_d.h"
30 #include "dce/dce_11_0_sh_mask.h"
32 #include "dce/dce_opp.h"
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| /Linux-v5.15/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/ |
| D | dce110_clk_mgr.c | 29 #include "dce/dce_11_0_d.h"
30 #include "dce/dce_11_0_sh_mask.h"
183 context->bw_ctx.bw.dce.all_displays_in_sync; in dce11_pplib_apply_display_requirements()
185 context->bw_ctx.bw.dce.nbp_state_change_enable == false; in dce11_pplib_apply_display_requirements()
187 context->bw_ctx.bw.dce.cpuc_state_change_enable == false; in dce11_pplib_apply_display_requirements()
189 context->bw_ctx.bw.dce.cpup_state_change_enable == false; in dce11_pplib_apply_display_requirements()
191 context->bw_ctx.bw.dce.blackout_recovery_time_us; in dce11_pplib_apply_display_requirements()
205 pp_display_cfg->min_memory_clock_khz = context->bw_ctx.bw.dce.yclk_khz in dce11_pplib_apply_display_requirements()
211 context->bw_ctx.bw.dce.sclk_khz); in dce11_pplib_apply_display_requirements()
224 = context->bw_ctx.bw.dce.sclk_deep_sleep_khz; in dce11_pplib_apply_display_requirements()
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| /Linux-v5.15/drivers/gpu/drm/amd/display/dc/dcn301/ |
| D | dcn301_dio_link_encoder.c | 125 /* For DCE 8.0 and 8.1, by design, UNIPHY is hardwired to DIG_BE. in dcn301_link_encoder_construct()
130 * For DCE 8.0, there are only max 6 UNIPHYs, we assume board design in dcn301_link_encoder_construct()
131 * and VBIOS will filter out 7 UNIPHY for DCE 8.0. in dcn301_link_encoder_construct()
132 * By this, adding DIGG should not hurt DCE 8.0. in dcn301_link_encoder_construct()
133 * This will let DCE 8.1 share DCE 8.0 as much as possible in dcn301_link_encoder_construct()
175 /* Override features with DCE-specific values */ in dcn301_link_encoder_construct()
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| /Linux-v5.15/include/uapi/linux/hdlc/ |
| D | ioctl.h | 10 #define CLOCK_INT 2 /* Internal TX and RX clock - DCE */
65 unsigned short dce; /* 1 for DCE (network side) operation */ member
83 unsigned short dce; /* 1 for DCE (network side) operation */ member
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| /Linux-v5.15/drivers/gpu/drm/amd/display/dc/dce/ |
| D | Makefile | 23 # Makefile for common 'dce' logic
29 DCE = dce_audio.o dce_stream_encoder.o dce_link_encoder.o dce_hwseq.o \ macro
35 AMD_DAL_DCE = $(addprefix $(AMDDALPATH)/dc/dce/,$(DCE))
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| D | dce_clk_mgr.c | 54 /* ClocksStateUltraLow - not expected to be used for DCE 8.0 */
202 /* raise clock state for HBR3/2 if required. Confirmed with HW DCE/DPCS in get_max_pixel_clock_for_all_paths()
227 if (context->bw_ctx.bw.dce.dispclk_khz > in dce_get_required_clocks_state()
237 < context->bw_ctx.bw.dce.dispclk_khz) in dce_get_required_clocks_state()
462 * the dce clock manager. This operation will overwrite the existing dprefclk
617 context->bw_ctx.bw.dce.all_displays_in_sync; in dce11_pplib_apply_display_requirements()
619 context->bw_ctx.bw.dce.nbp_state_change_enable == false; in dce11_pplib_apply_display_requirements()
621 context->bw_ctx.bw.dce.cpuc_state_change_enable == false; in dce11_pplib_apply_display_requirements()
623 context->bw_ctx.bw.dce.cpup_state_change_enable == false; in dce11_pplib_apply_display_requirements()
625 context->bw_ctx.bw.dce.blackout_recovery_time_us; in dce11_pplib_apply_display_requirements()
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| D | dce_link_encoder.c | 40 #include "dce/dce_11_0_d.h"
41 #include "dce/dce_11_0_sh_mask.h"
42 #include "dce/dce_11_0_enum.h"
661 /*In DCE 11, we are able to pre-program a Force SR register in dce110_psr_program_dp_dphy_fast_training()
853 /* For DCE 8.0 and 8.1, by design, UNIPHY is hardwired to DIG_BE. in dce110_link_encoder_construct()
858 * For DCE 8.0, there are only max 6 UNIPHYs, we assume board design in dce110_link_encoder_construct()
859 * and VBIOS will filter out 7 UNIPHY for DCE 8.0. in dce110_link_encoder_construct()
860 * By this, adding DIGG should not hurt DCE 8.0. in dce110_link_encoder_construct()
861 * This will let DCE 8.1 share DCE 8.0 as much as possible in dce110_link_encoder_construct()
901 /* Override features with DCE-specific values */ in dce110_link_encoder_construct()
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| /Linux-v5.15/drivers/gpu/drm/amd/display/dc/dce100/ |
| D | dce100_resource.c | 39 #include "dce/dce_link_encoder.h"
40 #include "dce/dce_stream_encoder.h"
41 #include "dce/dce_mem_input.h"
42 #include "dce/dce_ipp.h"
43 #include "dce/dce_transform.h"
44 #include "dce/dce_opp.h"
45 #include "dce/dce_clock_source.h"
46 #include "dce/dce_audio.h"
47 #include "dce/dce_hwseq.h"
49 #include "dce/dce_panel_cntl.h"
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| /Linux-v5.15/drivers/tty/serial/ |
| D | icom.h | 70 u8 dce_resvd[20]; /* 1C8-1DB DCE Rsvd */
71 u8 dce_resvd21; /* 1DC DCE Rsvd (21st byte */
80 u8 dce_command; /* 1E7 dce command reg */
81 u8 dce_cmd_status; /* 1E8 dce command stat */
82 u8 x21_r1_ioff; /* 1E9 dce ready counter */
83 u8 x21_r0_ioff; /* 1EA dce not ready ctr */
84 u8 x21_ralt_ioff; /* 1EB dce CNR counter */
85 u8 x21_r1_ion; /* 1EC dce ready I on ctr */
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| /Linux-v5.15/drivers/gpu/drm/amd/display/dc/dcn30/ |
| D | dcn30_dio_link_encoder.c | 138 /* For DCE 8.0 and 8.1, by design, UNIPHY is hardwired to DIG_BE. in dcn30_link_encoder_construct()
143 * For DCE 8.0, there are only max 6 UNIPHYs, we assume board design in dcn30_link_encoder_construct()
144 * and VBIOS will filter out 7 UNIPHY for DCE 8.0. in dcn30_link_encoder_construct()
145 * By this, adding DIGG should not hurt DCE 8.0. in dcn30_link_encoder_construct()
146 * This will let DCE 8.1 share DCE 8.0 as much as possible in dcn30_link_encoder_construct()
188 /* Override features with DCE-specific values */ in dcn30_link_encoder_construct()
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| /Linux-v5.15/drivers/gpu/drm/amd/display/dc/dce60/ |
| D | dce60_resource.c | 28 #include "dce/dce_6_0_d.h"
29 #include "dce/dce_6_0_sh_mask.h"
42 #include "dce/dce_mem_input.h"
43 #include "dce/dce_link_encoder.h"
44 #include "dce/dce_stream_encoder.h"
45 #include "dce/dce_ipp.h"
46 #include "dce/dce_transform.h"
47 #include "dce/dce_opp.h"
48 #include "dce/dce_clock_source.h"
49 #include "dce/dce_audio.h"
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| /Linux-v5.15/drivers/gpu/drm/amd/display/dc/dce80/ |
| D | dce80_resource.c | 28 #include "dce/dce_8_0_d.h"
29 #include "dce/dce_8_0_sh_mask.h"
42 #include "dce/dce_mem_input.h"
43 #include "dce/dce_link_encoder.h"
44 #include "dce/dce_stream_encoder.h"
45 #include "dce/dce_ipp.h"
46 #include "dce/dce_transform.h"
47 #include "dce/dce_opp.h"
48 #include "dce/dce_clock_source.h"
49 #include "dce/dce_audio.h"
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| D | dce80_hw_sequencer.c | 31 #include "dce/dce_hwseq.h"
36 #include "dce/dce_8_0_d.h"
37 #include "dce/dce_8_0_sh_mask.h"
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| /Linux-v5.15/drivers/gpu/drm/amd/display/dc/dcn21/ |
| D | dcn21_link_encoder.c | 378 /* For DCE 8.0 and 8.1, by design, UNIPHY is hardwired to DIG_BE. in dcn21_link_encoder_construct()
383 * For DCE 8.0, there are only max 6 UNIPHYs, we assume board design in dcn21_link_encoder_construct()
384 * and VBIOS will filter out 7 UNIPHY for DCE 8.0. in dcn21_link_encoder_construct()
385 * By this, adding DIGG should not hurt DCE 8.0. in dcn21_link_encoder_construct()
386 * This will let DCE 8.1 share DCE 8.0 as much as possible in dcn21_link_encoder_construct()
428 /* Override features with DCE-specific values */ in dcn21_link_encoder_construct()
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| /Linux-v5.15/drivers/gpu/drm/amd/display/dc/dce120/ |
| D | dce120_resource.c | 43 #include "dce/dce_opp.h"
44 #include "dce/dce_clock_source.h"
45 #include "dce/dce_ipp.h"
46 #include "dce/dce_mem_input.h"
47 #include "dce/dce_panel_cntl.h"
51 #include "dce/dce_transform.h"
53 #include "dce/dce_audio.h"
54 #include "dce/dce_link_encoder.h"
55 #include "dce/dce_stream_encoder.h"
56 #include "dce/dce_hwseq.h"
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| D | dce120_hw_sequencer.c | 30 #include "dce/dce_hwseq.h"
34 #include "dce/dce_12_0_offset.h"
35 #include "dce/dce_12_0_sh_mask.h"
249 * @hws: DCE hardware sequencer object
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| /Linux-v5.15/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/ |
| D | dce60_clk_mgr.c | 43 #include "dce/dce_6_0_d.h"
44 #include "dce/dce_6_0_sh_mask.h"
74 /* ClocksStateUltraLow - not expected to be used for DCE 6.0 */
126 int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz; in dce60_update_clocks()
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| /Linux-v5.15/Documentation/filesystems/cifs/ |
| D | ksmbd.rst | 15 performance in userspace. So, DCE/RPC management that has historically resulted
34 currently DCE/RPC commands are identified to be handled through the user space.
59 NetServerGetInfo. Complete DCE/RPC response is prepared from the user space
105 DCE/RPC support Partially Supported. a few calls(NetShareEnumAll,
111 DCE/RPC management calls (and future support
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| /Linux-v5.15/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/ |
| D | dce_clk_mgr.c | 43 #include "dce/dce_8_0_d.h"
44 #include "dce/dce_8_0_sh_mask.h"
70 /* ClocksStateUltraLow - not expected to be used for DCE 8.0 */
183 /* raise clock state for HBR3/2 if required. Confirmed with HW DCE/DPCS in dce_get_max_pixel_clock_for_all_paths()
208 if (context->bw_ctx.bw.dce.dispclk_khz > in dce_get_required_clocks_state()
218 < context->bw_ctx.bw.dce.dispclk_khz) in dce_get_required_clocks_state()
401 int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz; in dce_update_clocks()
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| /Linux-v5.15/drivers/gpu/drm/amd/display/dc/dcn31/ |
| D | dcn31_dio_link_encoder.c | 274 /* For DCE 8.0 and 8.1, by design, UNIPHY is hardwired to DIG_BE. in dcn31_link_encoder_construct()
279 * For DCE 8.0, there are only max 6 UNIPHYs, we assume board design in dcn31_link_encoder_construct()
280 * and VBIOS will filter out 7 UNIPHY for DCE 8.0. in dcn31_link_encoder_construct()
281 * By this, adding DIGG should not hurt DCE 8.0. in dcn31_link_encoder_construct()
282 * This will let DCE 8.1 share DCE 8.0 as much as possible in dcn31_link_encoder_construct()
321 /* Override features with DCE-specific values */ in dcn31_link_encoder_construct()
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| /Linux-v5.15/drivers/gpu/drm/amd/display/dc/dcn20/ |
| D | dcn20_link_encoder.c | 436 /* For DCE 8.0 and 8.1, by design, UNIPHY is hardwired to DIG_BE. in dcn20_link_encoder_construct()
441 * For DCE 8.0, there are only max 6 UNIPHYs, we assume board design in dcn20_link_encoder_construct()
442 * and VBIOS will filter out 7 UNIPHY for DCE 8.0. in dcn20_link_encoder_construct()
443 * By this, adding DIGG should not hurt DCE 8.0. in dcn20_link_encoder_construct()
444 * This will let DCE 8.1 share DCE 8.0 as much as possible in dcn20_link_encoder_construct()
486 /* Override features with DCE-specific values */ in dcn20_link_encoder_construct()
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| /Linux-v5.15/drivers/net/wan/ |
| D | hdlc_fr.c | 11 DCE mode:
352 if (state(hdlc)->settings.dce) { in pvc_close()
462 int dce = state(hdlc)->settings.dce; in fr_lmi_send() local
468 if (dce && fullrep) { in fr_lmi_send()
489 data[i++] = dce ? LMI_STATUS : LMI_STATUS_ENQUIRY; in fr_lmi_send()
502 if (dce && fullrep) { in fr_lmi_send()
575 if (!state(hdlc)->settings.dce) in fr_set_link_state()
590 if (state(hdlc)->settings.dce) { in fr_timer()
615 if (state(hdlc)->settings.dce) { in fr_timer()
639 int dce = state(hdlc)->settings.dce; in fr_lmi_recv() local
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| /Linux-v5.15/drivers/gpu/drm/amd/pm/inc/ |
| D | smu7_common.h | 43 #include "dce/dce_10_0_d.h"
44 #include "dce/dce_10_0_sh_mask.h"
|
