| /Linux-v6.1/arch/powerpc/kernel/ |
| D | cacheinfo.c | 3 * Processor cache information made available to userspace via sysfs;
27 * - a "cache" kobject for the top-level directory
28 * - a list of "index" objects representing the cpu's local cache hierarchy
31 struct kobject *kobj; /* bare (not embedded) kobject for cache
36 /* "index" object: each cpu's cache directory has an index
37 * subdirectory corresponding to a cache object associated with the
43 struct cache *cache; member
47 * cache type */
52 /* Allow for both [di]-cache-line-size and
53 * [di]-cache-block-size properties. According to the PowerPC
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| /Linux-v6.1/fs/fscache/ |
| D | cache.c | 2 /* FS-Cache cache handling
8 #define FSCACHE_DEBUG_LEVEL CACHE
22 * Allocate a cache cookie.
26 struct fscache_cache *cache; in fscache_alloc_cache() local
28 cache = kzalloc(sizeof(*cache), GFP_KERNEL); in fscache_alloc_cache()
29 if (cache) { in fscache_alloc_cache()
31 cache->name = kstrdup(name, GFP_KERNEL); in fscache_alloc_cache()
32 if (!cache->name) { in fscache_alloc_cache()
33 kfree(cache); in fscache_alloc_cache()
37 refcount_set(&cache->ref, 1); in fscache_alloc_cache()
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| /Linux-v6.1/drivers/md/ |
| D | dm-cache-target.c | 10 #include "dm-cache-metadata.h"
23 #define DM_MSG_PREFIX "cache"
26 "A percentage of time allocated for copying to and/or from cache");
34 * cblock: index of a cache block
35 * promotion: movement of a block from origin to cache
36 * demotion: movement of a block from cache to origin
37 * migration: movement of a block between the origin and cache device,
240 * The block size of the device holding cache data must be
255 * dirty. If you lose the cache device you will lose data.
261 * Data is written to both cache and origin. Blocks are never
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| /Linux-v6.1/fs/cachefiles/ |
| D | cache.c | 2 /* Manage high-level VFS aspects of a cache.
14 * Bring a cache online.
16 int cachefiles_add_cache(struct cachefiles_cache *cache) in cachefiles_add_cache() argument
27 cache_cookie = fscache_acquire_cache(cache->tag); in cachefiles_add_cache()
32 ret = cachefiles_get_security_ID(cache); in cachefiles_add_cache()
36 cachefiles_begin_secure(cache, &saved_cred); in cachefiles_add_cache()
38 /* look up the directory at the root of the cache */ in cachefiles_add_cache()
39 ret = kern_path(cache->rootdirname, LOOKUP_DIRECTORY, &path); in cachefiles_add_cache()
43 cache->mnt = path.mnt; in cachefiles_add_cache()
48 pr_warn("File cache on idmapped mounts not supported"); in cachefiles_add_cache()
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|
| D | daemon.c | 61 int (*handler)(struct cachefiles_cache *cache, char *args);
86 * Prepare a cache for caching.
90 struct cachefiles_cache *cache; in cachefiles_daemon_open() local
102 /* allocate a cache record */ in cachefiles_daemon_open()
103 cache = kzalloc(sizeof(struct cachefiles_cache), GFP_KERNEL); in cachefiles_daemon_open()
104 if (!cache) { in cachefiles_daemon_open()
109 mutex_init(&cache->daemon_mutex); in cachefiles_daemon_open()
110 init_waitqueue_head(&cache->daemon_pollwq); in cachefiles_daemon_open()
111 INIT_LIST_HEAD(&cache->volumes); in cachefiles_daemon_open()
112 INIT_LIST_HEAD(&cache->object_list); in cachefiles_daemon_open()
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|
| /Linux-v6.1/tools/perf/pmu-events/arch/s390/cf_z16/ |
| D | extended.json | 7 … cache where the line was originally in a Read-Only state in the cache but has been updated to be …
14 …on Lookaside Buffer 2 (TLB2) and the request was made by the Level-1 Data cache. This is a replace…
21 … request made by the Level-1 Data cache. Incremented by one for every TLB2 miss in progress for th…
42 …ion Lookaside Buffer 2 (TLB2) and the request was made by the instruction cache. This is a replace…
49 …ade by the Level-1 Instruction cache. Incremented by one for every TLB2 miss in progress for the L…
91 …"PublicDescription": "Increments by one for any cycle where a level-1 cache or level-2 TLB miss is…
97 "BriefDescription": "Directory Write Level 1 Data Cache from Cache",
98 …ory write to the Level-1 Data cache directory where the returned cache line was sourced from the r…
104 "BriefDescription": "Directory Write Level 1 Data Cache from Cache with Intervention",
105 …ory write to the Level-1 Data cache directory where the returned cache line was sourced from the r…
[all …]
|
| /Linux-v6.1/arch/arm64/boot/dts/amd/ |
| D | amd-seattle-cpus.dtsi | 49 i-cache-size = <0xC000>;
50 i-cache-line-size = <64>;
51 i-cache-sets = <256>;
52 d-cache-size = <0x8000>;
53 d-cache-line-size = <64>;
54 d-cache-sets = <256>;
55 l2-cache = <&L2_0>;
65 i-cache-size = <0xC000>;
66 i-cache-line-size = <64>;
67 i-cache-sets = <256>;
[all …]
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| /Linux-v6.1/arch/arm64/boot/dts/amazon/ |
| D | alpine-v3.dtsi | 28 d-cache-size = <0x8000>;
29 d-cache-line-size = <64>;
30 d-cache-sets = <256>;
31 i-cache-size = <0xc000>;
32 i-cache-line-size = <64>;
33 i-cache-sets = <256>;
34 next-level-cache = <&cluster0_l2>;
42 d-cache-size = <0x8000>;
43 d-cache-line-size = <64>;
44 d-cache-sets = <256>;
[all …]
|
| /Linux-v6.1/fs/ |
| D | mbcache.c | 16 * Ext2 and ext4 use this cache for deduplication of extended attribute blocks.
21 * identifies a cache entry.
33 /* Maximum entries in cache to avoid degrading hash too much */
38 /* Number of entries in cache */
41 /* Work for shrinking when the cache has too many entries */
47 static unsigned long mb_cache_shrink(struct mb_cache *cache,
50 static inline struct hlist_bl_head *mb_cache_entry_head(struct mb_cache *cache, in mb_cache_entry_head() argument
53 return &cache->c_hash[hash_32(key, cache->c_bucket_bits)]; in mb_cache_entry_head()
58 * in cache
63 * mb_cache_entry_create - create entry in cache
[all …]
|
| /Linux-v6.1/Documentation/devicetree/bindings/powerpc/fsl/ |
| D | l2cache.txt | 1 Freescale L2 Cache Controller
3 L2 cache is present in Freescale's QorIQ and QorIQ Qonverge platforms.
4 The cache bindings explained below are Devicetree Specification compliant
9 "fsl,b4420-l2-cache-controller"
10 "fsl,b4860-l2-cache-controller"
11 "fsl,bsc9131-l2-cache-controller"
12 "fsl,bsc9132-l2-cache-controller"
13 "fsl,c293-l2-cache-controller"
14 "fsl,mpc8536-l2-cache-controller"
15 "fsl,mpc8540-l2-cache-controller"
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| /Linux-v6.1/fs/squashfs/ |
| D | cache.c | 8 * cache.c
15 * This file implements a generic cache implementation used for both caches,
16 * plus functions layered ontop of the generic cache implementation to
19 * To avoid out of memory and fragmentation issues with vmalloc the cache
22 * It should be noted that the cache is not used for file datablocks, these
23 * are decompressed and cached in the page-cache in the normal way. The
24 * cache is only used to temporarily cache fragment and metadata blocks
49 * Look-up block in cache, and increment usage count. If not in cache, read
53 struct squashfs_cache *cache, u64 block, int length) in squashfs_cache_get() argument
58 spin_lock(&cache->lock); in squashfs_cache_get()
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| /Linux-v6.1/tools/perf/pmu-events/arch/arm64/arm/cortex-a65-e1/ |
| D | cache.json | 111 …"Level 1 data cache refill started due to prefetch. Counts any linefills from the prefetcher which…
114 …"Level 1 data cache refill started due to prefetch. Counts any linefills from the prefetcher which…
117 …cache refill due to prefetch. +//0 If the core is configured with a per-core L2 cache: This event …
120 …cache refill due to prefetch. +//0 If the core is configured with a per-core L2 cache: This event …
123 …cache refill due to prefetch. This event counts any linefills from the hardware prefetcher which c…
126 …cache refill due to prefetch. This event counts any linefills from the hardware prefetcher which c…
141 … 2 cache write streaming mode. This event counts for each cycle where the core is in write-streami…
144 … 2 cache write streaming mode. This event counts for each cycle where the core is in write-streami…
147 … 3 cache write streaming mode. This event counts for each cycle where the core is in write-streami…
150 … 3 cache write streaming mode. This event counts for each cycle where the core is in write-streami…
[all …]
|
| /Linux-v6.1/mm/ |
| D | swap_slots.c | 3 * Manage cache of swap slots to be used for and returned from
25 * The swap slots cache is protected by a mutex instead of
43 /* Serialize swap slots cache enable/disable operations */
106 /* if global pool of slot caches too low, deactivate cache */ in check_cache_active()
115 struct swap_slots_cache *cache; in alloc_swap_slot_cache() local
136 cache = &per_cpu(swp_slots, cpu); in alloc_swap_slot_cache()
137 if (cache->slots || cache->slots_ret) { in alloc_swap_slot_cache()
138 /* cache already allocated */ in alloc_swap_slot_cache()
147 if (!cache->lock_initialized) { in alloc_swap_slot_cache()
148 mutex_init(&cache->alloc_lock); in alloc_swap_slot_cache()
[all …]
|
| /Linux-v6.1/Documentation/devicetree/bindings/arm/socionext/ |
| D | socionext,uniphier-system-cache.yaml | 4 $id: http://devicetree.org/schemas/arm/socionext/socionext,uniphier-system-cache.yaml#
7 title: UniPhier outer cache controller
10 UniPhier ARM 32-bit SoCs are integrated with a full-custom outer cache
11 controller system. All of them have a level 2 cache controller, and some
12 have a level 3 cache controller as well.
19 const: socionext,uniphier-system-cache
29 Interrupts can be used to notify the completion of cache operations.
35 cache-unified: true
37 cache-size: true
39 cache-sets: true
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|
| /Linux-v6.1/fs/nfs/ |
| D | nfs42xattr.c | 6 * User extended attribute client side cache functions.
21 * a cache structure attached to NFS inodes. This structure is allocated
22 * when needed, and freed when the cache is zapped.
24 * The cache structure contains as hash table of entries, and a pointer
25 * to a special-cased entry for the listxattr cache.
28 * counting. The cache entries use a similar refcounting scheme.
30 * This makes freeing a cache, both from the shrinker and from the
31 * zap cache path, easy. It also means that, in current use cases,
40 * Two shrinkers deal with the cache entries themselves: one for
45 * The other shrinker frees the cache structures themselves.
[all …]
|
| /Linux-v6.1/tools/perf/pmu-events/arch/s390/cf_z13/ |
| D | extended.json | 7 … cache where the line was originally in a Read-Only state in the cache but has been updated to be …
42 …rectory write to the Level-1 Data cache directory where the returned cache line was sourced from t…
63 …te to the Level-1 Instruction cache directory where the returned cache line was sourced from the L…
105 …"PublicDescription": "Increments by one for any cycle where a Level-1 cache or Level-1 TLB miss is…
112 …ectory write to the Level-1 Data cache directory where the returned cache line was sourced from an…
119 …ectory write to the Level-1 Data cache directory where the returned cache line was sourced from an…
126 …ectory write to the Level-1 Data cache directory where the returned cache line was sourced from an…
133 …ectory write to the Level-1 Data cache directory where the returned cache line was sourced from an…
140 …ectory write to the Level-1 Data cache directory where the returned cache line was sourced from an…
147 …ctory write to the Level-1 Data cache directory where the returned cache line was sourced from an …
[all …]
|
| /Linux-v6.1/Documentation/filesystems/caching/ |
| D | backend-api.rst | 4 Cache Backend API
7 The FS-Cache system provides an API by which actual caches can be supplied to
8 FS-Cache for it to then serve out to network filesystems and other interested
11 #include <linux/fscache-cache.h>.
17 Interaction with the API is handled on three levels: cache, volume and data
23 Cache cookie struct fscache_cache
28 Cookies are used to provide some filesystem data to the cache, manage state and
29 pin the cache during access in addition to acting as reference points for the
34 The cache backend and the network filesystem can both ask for cache cookies -
39 Cache Cookies
[all …]
|
| /Linux-v6.1/tools/perf/pmu-events/arch/arm64/arm/cortex-a510/ |
| D | cache.json | 102 …cache refill due to prefetch. If the complex is configured with a per-complex L2 cache, this event…
105 …cache refill due to prefetch. If the complex is configured with a per-complex L2 cache, this event…
108 …": "L1 data cache refill due to prefetch. This event counts any linefills from the prefetcher that…
111 …": "L1 data cache refill due to prefetch. This event counts any linefills from the prefetcher that…
114 …2 cache write streaming mode. This event counts for each cycle where the core is in write streamin…
117 …2 cache write streaming mode. This event counts for each cycle where the core is in write streamin…
120 …"PublicDescription": "L1 data cache entering write streaming mode. This event counts for each entr…
123 …"BriefDescription": "L1 data cache entering write streaming mode. This event counts for each entry…
126 …cache write streaming mode. This event counts for each cycle where the core is in write streaming …
129 …cache write streaming mode. This event counts for each cycle where the core is in write streaming …
[all …]
|
| /Linux-v6.1/drivers/acpi/acpica/ |
| D | utcache.c | 4 * Module Name: utcache - local cache allocation routines
21 * PARAMETERS: cache_name - Ascii name for the cache
23 * max_depth - Maximum depth of the cache (in objects)
24 * return_cache - Where the new cache object is returned
28 * DESCRIPTION: Create a cache object
36 struct acpi_memory_list *cache; in acpi_os_create_cache() local
44 /* Create the cache object */ in acpi_os_create_cache()
46 cache = acpi_os_allocate(sizeof(struct acpi_memory_list)); in acpi_os_create_cache()
47 if (!cache) { in acpi_os_create_cache()
51 /* Populate the cache object and return it */ in acpi_os_create_cache()
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|
| /Linux-v6.1/arch/arm64/boot/dts/ti/ |
| D | k3-am654.dtsi | 41 i-cache-size = <0x8000>;
42 i-cache-line-size = <64>;
43 i-cache-sets = <256>;
44 d-cache-size = <0x8000>;
45 d-cache-line-size = <64>;
46 d-cache-sets = <128>;
47 next-level-cache = <&L2_0>;
55 i-cache-size = <0x8000>;
56 i-cache-line-size = <64>;
57 i-cache-sets = <256>;
[all …]
|
| /Linux-v6.1/tools/perf/pmu-events/arch/s390/cf_z14/ |
| D | extended.json | 7 … cache where the line was originally in a Read-Only state in the cache but has been updated to be …
14 …ranslation Lookaside Buffer 2 (TLB2) and the request was made by the data cache. This is a replace…
21 …ss for a request made by the data cache. Incremented by one for every TLB2 miss in progress for th…
42 …rectory write to the Level-1 Data cache directory where the returned cache line was sourced from t…
49 …ion Lookaside Buffer 2 (TLB2) and the request was made by the instruction cache. This is a replace…
56 …equest made by the instruction cache. Incremented by one for every TLB2 miss in progress for the L…
63 …te to the Level-1 Instruction cache directory where the returned cache line was sourced from the L…
105 …"PublicDescription": "Increments by one for any cycle where a level-1 cache or level-2 TLB miss is…
112 …ectory write to the Level-1 Data cache directory where the returned cache line was sourced from an…
119 …licDescription": "A directory write to the Level-1 Data cache directory where the returned cache l…
[all …]
|
| /Linux-v6.1/tools/perf/pmu-events/arch/arm64/arm/cortex-a55/ |
| D | cache.json | 105 …cache refill due to prefetch. This event counts any linefills from the hardware prefetcher which c…
108 …cache refill due to prefetch. This event counts any linefills from the hardware prefetcher which c…
111 …cache refill due to prefetch. +//0 If the core is configured with a per-core L2 cache: This event …
114 …cache refill due to prefetch. +//0 If the core is configured with a per-core L2 cache: This event …
117 …Level 1 data cache refill due to prefetch. This event counts any linefills from the prefetcher whi…
120 …Level 1 data cache refill due to prefetch. This event counts any linefills from the prefetcher whi…
123 … 2 cache write streaming mode. This event counts for each cycle where the core is in write-streami…
126 … 2 cache write streaming mode. This event counts for each cycle where the core is in write-streami…
129 …"PublicDescription": "Level 1 data cache entering write streaming mode.This event counts for each …
132 …"BriefDescription": "Level 1 data cache entering write streaming mode.This event counts for each e…
[all …]
|
| /Linux-v6.1/fs/btrfs/tests/ |
| D | free-space-tree-tests.c | 21 struct btrfs_block_group *cache, in __check_free_space_extents() argument
34 info = search_free_space_info(trans, cache, path, 0); in __check_free_space_extents()
51 end = cache->start + cache->length; in __check_free_space_extents()
59 bit = free_space_test_bit(cache, path, offset); in __check_free_space_extents()
108 struct btrfs_block_group *cache, in check_free_space_extents() argument
117 info = search_free_space_info(trans, cache, path, 0); in check_free_space_extents()
126 ret = __check_free_space_extents(trans, fs_info, cache, path, extents, in check_free_space_extents()
133 ret = convert_free_space_to_extents(trans, cache, path); in check_free_space_extents()
139 ret = convert_free_space_to_bitmaps(trans, cache, path); in check_free_space_extents()
145 return __check_free_space_extents(trans, fs_info, cache, path, extents, in check_free_space_extents()
[all …]
|
| /Linux-v6.1/tools/perf/pmu-events/arch/s390/cf_z15/ |
| D | extended.json | 7 … cache where the line was originally in a Read-Only state in the cache but has been updated to be …
14 …ranslation Lookaside Buffer 2 (TLB2) and the request was made by the data cache. This is a replace…
21 …ss for a request made by the data cache. Incremented by one for every TLB2 miss in progress for th…
42 …rectory write to the Level-1 Data cache directory where the returned cache line was sourced from t…
49 …ion Lookaside Buffer 2 (TLB2) and the request was made by the instruction cache. This is a replace…
56 …equest made by the instruction cache. Incremented by one for every TLB2 miss in progress for the L…
63 …te to the Level-1 Instruction cache directory where the returned cache line was sourced from the L…
105 …"PublicDescription": "Increments by one for any cycle where a level-1 cache or level-2 TLB miss is…
112 …ectory write to the Level-1 Data cache directory where the returned cache line was sourced from an…
119 …licDescription": "A directory write to the Level-1 Data cache directory where the returned cache l…
[all …]
|
| /Linux-v6.1/tools/perf/pmu-events/arch/x86/goldmont/ |
| D | cache.json | 12 "BriefDescription": "L1 Cache evictions for dirty data",
17 …"PublicDescription": "Counts when a modified (dirty) cache line is evicted from the data L1 cache …
27 …s not the same as the total number of cycles spent retrieving instruction cache lines from the mem…
41 "BriefDescription": "L2 cache request misses",
46 …"PublicDescription": "Counts memory requests originating from the core that miss in the L2 cache.",
51 "BriefDescription": "L2 cache requests",
56 …": "Counts memory requests originating from the core that reference a cache line in the L2 cache.",
68 … loads are ignored. A memory load can hit (or miss) the L1 cache, hit (or miss) the L2 cache, hit…
80 …cache line containing the data was in the modified state of another core or modules cache (HITM). …
85 "BriefDescription": "Load uops retired that hit L1 data cache (Precise event capable)",
[all …]
|
