/Linux-v6.6/drivers/media/platform/renesas/rzg2l-cru/ |
D | rzg2l-video.c | 3 * Driver for Renesas RZ/G2L CRU 21 #include "rzg2l-cru.h" 23 /* HW CRU Registers Definition */ 25 /* CRU Control Register */ 29 /* CRU Interrupt Enable Register */ 33 /* CRU Interrupt Status Register */ 37 /* CRU Reset Register */ 41 /* Memory Bank Base Address (Lower) Register for CRU Image Data */ 44 /* Memory Bank Base Address (Higher) Register for CRU Image Data */ 47 /* Memory Bank Enable Register for CRU Image Data */ [all …]
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D | rzg2l-core.c | 3 * Driver for Renesas RZ/G2L CRU 24 #include "rzg2l-cru.h" 41 struct rzg2l_cru_dev *cru = notifier_to_cru(notifier); in rzg2l_cru_group_notify_complete() local 45 ret = rzg2l_cru_ip_subdev_register(cru); in rzg2l_cru_group_notify_complete() 49 ret = v4l2_device_register_subdev_nodes(&cru->v4l2_dev); in rzg2l_cru_group_notify_complete() 51 dev_err(cru->dev, "Failed to register subdev nodes\n"); in rzg2l_cru_group_notify_complete() 55 ret = rzg2l_cru_video_register(cru); in rzg2l_cru_group_notify_complete() 60 * CRU can be connected either to CSI2 or PARALLEL device in rzg2l_cru_group_notify_complete() 63 * Create media device link between CSI-2 <-> CRU IP in rzg2l_cru_group_notify_complete() 65 source = &cru->csi.subdev->entity; in rzg2l_cru_group_notify_complete() [all …]
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D | rzg2l-ip.c | 3 * Driver for Renesas RZ/G2L CRU 8 #include "rzg2l-cru.h" 36 struct v4l2_mbus_framefmt *rzg2l_cru_ip_get_src_fmt(struct rzg2l_cru_dev *cru) in rzg2l_cru_ip_get_src_fmt() argument 41 state = v4l2_subdev_lock_and_get_active_state(&cru->ip.subdev); in rzg2l_cru_ip_get_src_fmt() 42 fmt = v4l2_subdev_get_pad_format(&cru->ip.subdev, state, 1); in rzg2l_cru_ip_get_src_fmt() 50 struct rzg2l_cru_dev *cru; in rzg2l_cru_ip_s_stream() local 54 cru = v4l2_get_subdevdata(sd); in rzg2l_cru_ip_s_stream() 57 ret = v4l2_subdev_call(cru->ip.remote, video, s_stream, enable); in rzg2l_cru_ip_s_stream() 61 ret = v4l2_subdev_call(cru->ip.remote, video, post_streamoff); in rzg2l_cru_ip_s_stream() 66 rzg2l_cru_stop_image_processing(cru); in rzg2l_cru_ip_s_stream() [all …]
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D | rzg2l-cru.h | 3 * Driver for Renesas RZ/G2L CRU 61 * struct rzg2l_cru_dev - Renesas CRU device structure 64 * @info: info about CRU instance 69 * @vclk: CRU Main clock 73 * @vdev: V4L2 video device associated with CRU 136 void rzg2l_cru_vclk_unprepare(struct rzg2l_cru_dev *cru); 137 int rzg2l_cru_vclk_prepare(struct rzg2l_cru_dev *cru); 139 int rzg2l_cru_start_image_processing(struct rzg2l_cru_dev *cru); 140 void rzg2l_cru_stop_image_processing(struct rzg2l_cru_dev *cru); 142 int rzg2l_cru_dma_register(struct rzg2l_cru_dev *cru); [all …]
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/Linux-v6.6/arch/arm64/boot/dts/rockchip/ |
D | rk3588s.dtsi | 6 #include <dt-bindings/clock/rockchip,rk3588-cru.h> 10 #include <dt-bindings/reset/rockchip,rk3588-cru.h> 406 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&cru ACLK_USB>, <&u2phy2>; 417 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&cru ACLK_USB>, <&u2phy2>; 428 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&cru ACLK_USB>, <&u2phy3>; 439 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&cru ACLK_USB>, <&u2phy3>; 476 resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>; 478 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; 501 resets = <&cru SRST_OTGPHY_U2_1>, <&cru SRST_P_USB2PHY_U2_1_GRF0>; 503 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; [all …]
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D | rk3588.dtsi | 24 clocks = <&cru MCLK_I2S8_8CH_TX>, <&cru MCLK_I2S8_8CH_TX>, <&cru HCLK_I2S8_8CH>; 26 assigned-clocks = <&cru CLK_I2S8_8CH_TX_SRC>; 27 assigned-clock-parents = <&cru PLL_AUPLL>; 31 resets = <&cru SRST_M_I2S8_8CH_TX>; 41 clocks = <&cru MCLK_I2S6_8CH_TX>, <&cru MCLK_I2S6_8CH_TX>, <&cru HCLK_I2S6_8CH>; 43 assigned-clocks = <&cru CLK_I2S6_8CH_TX_SRC>; 44 assigned-clock-parents = <&cru PLL_AUPLL>; 48 resets = <&cru SRST_M_I2S6_8CH_TX>; 58 clocks = <&cru MCLK_I2S7_8CH_RX>, <&cru MCLK_I2S7_8CH_RX>, <&cru HCLK_I2S7_8CH>; 60 assigned-clocks = <&cru CLK_I2S7_8CH_RX_SRC>; [all …]
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D | rk356x.dtsi | 6 #include <dt-bindings/clock/rk3568-cru.h> 257 clocks = <&cru ACLK_SATA1>, <&cru CLK_SATA1_PMALIVE>, 258 <&cru CLK_SATA1_RXOOB>; 271 clocks = <&cru ACLK_SATA2>, <&cru CLK_SATA2_PMALIVE>, 272 <&cru CLK_SATA2_RXOOB>; 286 clocks = <&cru CLK_USB3OTG0_REF>, <&cru CLK_USB3OTG0_SUSPEND>, 287 <&cru ACLK_USB3OTG0>; 293 resets = <&cru SRST_USB3OTG0>; 302 clocks = <&cru CLK_USB3OTG1_REF>, <&cru CLK_USB3OTG1_SUSPEND>, 303 <&cru ACLK_USB3OTG1>; [all …]
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D | rk3399.dtsi | 6 #include <dt-bindings/clock/rk3399-cru.h> 75 clocks = <&cru ARMCLKL>; 87 clocks = <&cru ARMCLKL>; 99 clocks = <&cru ARMCLKL>; 111 clocks = <&cru ARMCLKL>; 123 clocks = <&cru ARMCLKB>; 141 clocks = <&cru ARMCLKB>; 185 clocks = <&cru SCLK_DDRC>; 232 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>, 233 <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>; [all …]
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D | rk3328.dtsi | 6 #include <dt-bindings/clock/rk3328-cru.h> 42 clocks = <&cru ARMCLK>; 55 clocks = <&cru ARMCLK>; 68 clocks = <&cru ARMCLK>; 81 clocks = <&cru ARMCLK>; 217 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>; 229 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>; 241 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>; 253 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>; 266 clocks = <&cru SCLK_PDM>, <&cru HCLK_PDM>; [all …]
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D | rk3368.dtsi | 6 #include <dt-bindings/clock/rk3368-cru.h> 183 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 184 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 188 resets = <&cru SRST_MMC0>; 197 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>, 198 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>; 202 resets = <&cru SRST_SDIO0>; 211 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 212 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 216 resets = <&cru SRST_EMMC>; [all …]
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D | px30.dtsi | 6 #include <dt-bindings/clock/px30-cru.h> 47 clocks = <&cru ARMCLK>; 59 clocks = <&cru ARMCLK>; 71 clocks = <&cru ARMCLK>; 83 clocks = <&cru ARMCLK>; 270 clocks = <&cru HCLK_HOST>, 271 <&cru HCLK_OTG>, 272 <&cru SCLK_OTG_ADP>; 278 clocks = <&cru HCLK_SDMMC>, 279 <&cru SCLK_SDMMC>; [all …]
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D | rk3568.dtsi | 14 clocks = <&cru ACLK_SATA0>, <&cru CLK_SATA0_PMALIVE>, 15 <&cru CLK_SATA0_RXOOB>; 55 <&cru PCLK_PCIE30PHY>; 57 resets = <&cru SRST_PCIE30PHY>; 68 clocks = <&cru ACLK_PCIE30X1_MST>, <&cru ACLK_PCIE30X1_SLV>, 69 <&cru ACLK_PCIE30X1_DBI>, <&cru PCLK_PCIE30X1>, 70 <&cru CLK_PCIE30X1_AUX_NDFT>; 102 resets = <&cru SRST_PCIE30X1_POWERUP>; 121 clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>, 122 <&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>, [all …]
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D | rk3308.dtsi | 7 #include <dt-bindings/clock/rk3308-cru.h> 46 clocks = <&cru ARMCLK>; 191 assigned-clocks = <&cru USB480M>; 193 clocks = <&cru SCLK_USBPHY_REF>; 235 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>; 248 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; 261 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; 274 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; 287 clocks = <&cru PCLK_WDT>; 296 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; [all …]
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/Linux-v6.6/arch/arm/boot/dts/rockchip/ |
D | rv1126.dtsi | 6 #include <dt-bindings/clock/rockchip,rv1126-cru.h> 35 clocks = <&cru ARMCLK>; 43 clocks = <&cru ARMCLK>; 51 clocks = <&cru ARMCLK>; 59 clocks = <&cru ARMCLK>; 178 clocks = <&cru HCLK_EMMC>, 179 <&cru CLK_EMMC>, 180 <&cru HCLK_NANDC>, 181 <&cru CLK_NANDC>, 182 <&cru HCLK_SFC>, [all …]
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D | rk322x.dtsi | 7 #include <dt-bindings/clock/rk3228-cru.h> 32 resets = <&cru SRST_CORE0>; 36 clocks = <&cru ARMCLK>; 44 resets = <&cru SRST_CORE1>; 54 resets = <&cru SRST_CORE2>; 64 resets = <&cru SRST_CORE3>; 140 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>; 153 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>; 163 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>; 177 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>; [all …]
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D | rk3288.dtsi | 7 #include <dt-bindings/clock/rk3288-cru.h> 61 resets = <&cru SRST_CORE0>; 65 clocks = <&cru ARMCLK>; 72 resets = <&cru SRST_CORE1>; 76 clocks = <&cru ARMCLK>; 83 resets = <&cru SRST_CORE2>; 87 clocks = <&cru ARMCLK>; 94 resets = <&cru SRST_CORE3>; 98 clocks = <&cru ARMCLK>; 199 clocks = <&cru PCLK_TIMER>, <&xin24m>; [all …]
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D | rk3xxx.dtsi | 42 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>; 44 assigned-clocks = <&cru ACLK_GPU>; 46 resets = <&cru SRST_GPU>; 56 clocks = <&cru ACLK_VDPU>, <&cru HCLK_VDPU>, 57 <&cru ACLK_VEPU>, <&cru HCLK_VEPU>; 78 clocks = <&cru CORE_PERI>; 92 clocks = <&cru CORE_PERI>; 110 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 121 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 169 clocks = <&cru HCLK_OTG0>; [all …]
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D | rk3066a.dtsi | 9 #include <dt-bindings/clock/rk3066a-cru.h> 36 clocks = <&cru ARMCLK>; 68 clocks = <&cru ACLK_LCDC0>, 69 <&cru DCLK_LCDC0>, 70 <&cru HCLK_LCDC0>; 73 resets = <&cru SRST_LCDC0_AXI>, 74 <&cru SRST_LCDC0_AHB>, 75 <&cru SRST_LCDC0_DCLK>; 94 clocks = <&cru ACLK_LCDC1>, 95 <&cru DCLK_LCDC1>, [all …]
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D | rk3036.dtsi | 7 #include <dt-bindings/clock/rk3036-cru.h> 41 resets = <&cru SRST_CORE0>; 47 clocks = <&cru ARMCLK>; 54 resets = <&cru SRST_CORE1>; 111 assigned-clocks = <&cru SCLK_GPU>; 113 clocks = <&cru SCLK_GPU>, <&cru SCLK_GPU>; 116 resets = <&cru SRST_GPU>; 125 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; 135 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; 145 clocks = <&cru ACLK_LCDC>, <&cru SCLK_LCDC>, <&cru HCLK_LCDC>; [all …]
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D | rv1108.dtsi | 6 #include <dt-bindings/clock/rv1108-cru.h> 36 clocks = <&cru ARMCLK>; 103 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 118 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 133 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 147 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; 161 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; 175 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; 187 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>; 200 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; [all …]
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D | rk3188.dtsi | 9 #include <dt-bindings/clock/rk3188-cru.h> 27 clocks = <&cru ARMCLK>; 29 resets = <&cru SRST_CORE0>; 37 resets = <&cru SRST_CORE1>; 45 resets = <&cru SRST_CORE2>; 53 resets = <&cru SRST_CORE3>; 119 clocks = <&cru ACLK_LCDC0>, <&cru DCLK_LCDC0>, <&cru HCLK_LCDC0>; 122 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>; 136 clocks = <&cru ACLK_LCDC1>, <&cru DCLK_LCDC1>, <&cru HCLK_LCDC1>; 139 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>; [all …]
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D | rk3128.dtsi | 6 #include <dt-bindings/clock/rk3128-cru.h> 36 clocks = <&cru ARMCLK>; 101 clocks = <&cru HCLK_OTG>; 131 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 132 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 138 resets = <&cru SRST_SDMMC>; 147 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 148 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 154 resets = <&cru SRST_SDIO>; 163 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, [all …]
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/Linux-v6.6/Documentation/devicetree/bindings/phy/ |
D | phy-rockchip-typec.txt | 11 - assigned-clocks: main clock, should be <&cru SCLK_UPHY0_TCPDCORE> or 12 <&cru SCLK_UPHY1_TCPDCORE>; 43 clocks = <&cru SCLK_UPHY0_TCPDCORE>, 44 <&cru SCLK_UPHY0_TCPDPHY_REF>; 46 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>; 48 resets = <&cru SRST_UPHY0>, 49 <&cru SRST_UPHY0_PIPE_L00>, 50 <&cru SRST_P_UPHY0_TCPHY>; 67 clocks = <&cru SCLK_UPHY1_TCPDCORE>, 68 <&cru SCLK_UPHY1_TCPDPHY_REF>; [all …]
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/Linux-v6.6/Documentation/devicetree/bindings/pci/ |
D | rockchip,rk3399-pcie-ep.yaml | 42 #include <dt-bindings/clock/rk3399-cru.h> 52 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>, 53 <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>; 58 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>, 59 <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE> , 60 <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, <&cru SRST_A_PCIE>;
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/Linux-v6.6/Documentation/devicetree/bindings/usb/ |
D | rockchip,rk3399-dwc3.yaml | 73 #include <dt-bindings/clock/rk3399-cru.h> 86 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>, 87 <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>, 88 <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>; 92 resets = <&cru SRST_A_USB3_OTG0>; 99 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru ACLK_USB3OTG0>, 100 <&cru SCLK_USB3OTG0_SUSPEND>;
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