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Searched full:clk_top_msdc50_0_h_sel (Results 1 – 6 of 6) sorted by relevance

/Linux-v5.15/Documentation/devicetree/bindings/mmc/
Dmtk-sd.yaml164 <&topckgen CLK_TOP_MSDC50_0_H_SEL>;
/Linux-v5.15/include/dt-bindings/clock/
Dmt8173-clk.h105 #define CLK_TOP_MSDC50_0_H_SEL 95 macro
Dmt8192-clk.h35 #define CLK_TOP_MSDC50_0_H_SEL 23 macro
/Linux-v5.15/drivers/clk/mediatek/
Dclk-mt8173.c558 MUX_GATE(CLK_TOP_MSDC50_0_H_SEL, "msdc50_0_h_sel", msdc50_0_h_parents, 0x0070, 8, 3, 15),
Dclk-mt8192.c762 MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_H_SEL, "msdc50_0_h_sel",
/Linux-v5.15/arch/arm64/boot/dts/mediatek/
Dmt8173.dtsi893 <&topckgen CLK_TOP_MSDC50_0_H_SEL>;