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/Linux-v5.10/drivers/clk/samsung/
Dclk-exynos-clkout.c35 static struct exynos_clkout *clkout; variable
39 clkout->pmu_debug_save = readl(clkout->reg + EXYNOS_PMU_DEBUG_REG); in exynos_clkout_suspend()
46 writel(clkout->pmu_debug_save, clkout->reg + EXYNOS_PMU_DEBUG_REG); in exynos_clkout_resume()
62 clkout = kzalloc(struct_size(clkout, data.hws, EXYNOS_CLKOUT_NR_CLKS), in exynos_clkout_init()
64 if (!clkout) in exynos_clkout_init()
67 spin_lock_init(&clkout->slock); in exynos_clkout_init()
73 snprintf(name, sizeof(name), "clkout%d", i); in exynos_clkout_init()
87 clkout->reg = of_iomap(node, 0); in exynos_clkout_init()
88 if (!clkout->reg) in exynos_clkout_init()
91 clkout->gate.reg = clkout->reg + EXYNOS_PMU_DEBUG_REG; in exynos_clkout_init()
[all …]
Dclk-s3c2410-dclk.c59 struct s3c24xx_clkout *clkout = to_s3c24xx_clkout(hw); in s3c24xx_clkout_get_parent() local
63 val = clkout->modify_misccr(0, 0) >> clkout->shift; in s3c24xx_clkout_get_parent()
64 val >>= clkout->shift; in s3c24xx_clkout_get_parent()
65 val &= clkout->mask; in s3c24xx_clkout_get_parent()
75 struct s3c24xx_clkout *clkout = to_s3c24xx_clkout(hw); in s3c24xx_clkout_set_parent() local
77 clkout->modify_misccr((clkout->mask << clkout->shift), in s3c24xx_clkout_set_parent()
78 (index << clkout->shift)); in s3c24xx_clkout_set_parent()
94 struct s3c24xx_clkout *clkout; in s3c24xx_register_clkout() local
101 /* allocate the clkout */ in s3c24xx_register_clkout()
102 clkout = kzalloc(sizeof(*clkout), GFP_KERNEL); in s3c24xx_register_clkout()
[all …]
/Linux-v5.10/include/linux/platform_data/
Dsi5351.h36 * @SI5351_CLKOUT_SRC_MSYNTH_N: clkout N source clock is multisynth N
37 * @SI5351_CLKOUT_SRC_MSYNTH_0_4: clkout N source clock is multisynth 0 (N<4)
39 * @SI5351_CLKOUT_SRC_XTAL: clkout N source clock is XTAL
40 * @SI5351_CLKOUT_SRC_CLKIN: clkout N source clock is CLKIN (Si5351C only)
85 * @clkout: clkout number
87 * @clkout_src: clkout source clock
88 * @pll_master: if true, clkout can also change pll rate
89 * @pll_reset: if true, clkout can reset its pll
91 * @rate: initial clkout rate, or default if 0
108 * @clkout: array of clkout configuration
[all …]
/Linux-v5.10/drivers/clk/
Dclk-si5351.c63 struct si5351_hw_data *clkout; member
797 * Si5351 clkout divider
917 __func__, clk_hw_get_name(&drvdata->clkout[num].hw), in _si5351_clkout_reset_pll()
935 if (pdata->clkout[hwdata->num].pll_reset) in si5351_clkout_prepare()
1039 /* clkout freqency is 8kHz - 160MHz */ in si5351_clkout_round_rate()
1120 /* powerup clkout */ in si5351_clkout_set_rate()
1211 /* per clkout properties */ in si5351_dt_parse()
1221 dev_err(&client->dev, "invalid clkout %d\n", num); in si5351_dt_parse()
1229 pdata->clkout[num].multisynth_src = in si5351_dt_parse()
1233 pdata->clkout[num].multisynth_src = in si5351_dt_parse()
[all …]
Dclk-rk808.c3 * Clkout driver for Rockchip RK808
202 .name = "rk808-clkout",
208 MODULE_DESCRIPTION("Clkout driver for the rk808 series PMICs");
211 MODULE_ALIAS("platform:rk808-clkout");
Dclk-lochnagar.c53 LN_PARENT("ln-cdc-clkout"),
54 LN_PARENT("ln-dsp-clkout"),
64 LN_PARENT("ln-cdc-clkout"),
65 LN_PARENT("ln-dsp-clkout"),
79 LN_PARENT("ln-spdif-clkout"),
Dclk-cdce706.c85 struct cdce706_hw_data clkout[6]; member
599 for (i = 0; i < ARRAY_SIZE(cdce->clkout); ++i) { in cdce706_register_clkouts()
605 cdce->clkout[i].parent = val & CDCE706_CLKOUT_DIVIDER_MASK; in cdce706_register_clkouts()
608 cdce->clkout[i].parent); in cdce706_register_clkouts()
611 return cdce706_register_hw(cdce, cdce->clkout, in cdce706_register_clkouts()
612 ARRAY_SIZE(cdce->clkout), in cdce706_register_clkouts()
622 if (idx >= ARRAY_SIZE(cdce->clkout)) { in of_clk_cdce_get()
627 return &cdce->clkout[idx].hw; in of_clk_cdce_get()
/Linux-v5.10/arch/arm/boot/dts/
Ddm814x-clocks.dtsi6 * "2.6.11 Connected Outputs of DPLLJ". Only clkout is
16 "481c5040.adpll.clkout",
28 "481c5080.adpll.clkout",
39 "481c50b0.adpll.clkout",
50 "481c50e0.adpll.clkout",
61 "481c5110.adpll.clkout",
72 "481c5140.adpll.clkout",
83 "481c5170.adpll.clkout",
94 "481c51a0.adpll.clkout",
105 "481c51d0.adpll.clkout",
[all …]
/Linux-v5.10/sound/soc/sh/rcar/
Dadg.c16 #define CLKOUT 0 macro
30 struct clk *clkout[CLKOUTMAX]; member
54 ((pos) = adg->clkout[i]); \
356 dev_dbg(dev, "CLKOUT is based on BRG%c (= %dHz)\n", in rsnd_adg_ssi_clk_try_start()
420 [CLKOUT] = "audio_clkout", in rsnd_adg_get_clkout()
464 if (of_get_property(np, "clkout-lr-asynchronous", NULL)) in rsnd_adg_get_clkout()
524 * for clkout in rsnd_adg_get_clkout()
527 clk = clk_register_fixed_rate(dev, clkout_name[CLKOUT], in rsnd_adg_get_clkout()
530 adg->clkout[CLKOUT] = clk; in rsnd_adg_get_clkout()
543 adg->clkout[i] = clk; in rsnd_adg_get_clkout()
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/Linux-v5.10/drivers/staging/clocking-wizard/
Dclk-xlnx-clock-wizard.c48 * @clkout: Output clocks
59 struct clk *clkout[WZRD_NUM_OUTPUTS]; member
244 clk_wzrd->clkout[i] = clk_register_fixed_factor in clk_wzrd_probe()
246 if (IS_ERR(clk_wzrd->clkout[i])) { in clk_wzrd_probe()
250 clk_unregister(clk_wzrd->clkout[j]); in clk_wzrd_probe()
253 ret = PTR_ERR(clk_wzrd->clkout[i]); in clk_wzrd_probe()
260 clk_wzrd->clk_data.clks = clk_wzrd->clkout; in clk_wzrd_probe()
261 clk_wzrd->clk_data.clk_num = ARRAY_SIZE(clk_wzrd->clkout); in clk_wzrd_probe()
300 clk_unregister(clk_wzrd->clkout[i]); in clk_wzrd_remove()
/Linux-v5.10/Documentation/devicetree/bindings/iio/adc/
Dst,stm32-dfsdm-adc.yaml38 dfsdm clock can also feed CLKOUT, when CLKOUT is used.
39 - description: audio clock can be used as an alternate to feed CLKOUT.
61 If not, SPI CLKOUT frequency will not be accurate.
136 - "CLKOUT": internal SPI clock (CLKOUT) (default)
140 enum: [ CLKIN, CLKOUT, CLKOUT_F, CLKOUT_R ]
303 st,adc-channel-clk-src = "CLKOUT";
/Linux-v5.10/drivers/video/fbdev/omap2/omapfb/dss/
Dhdmi_pll.c42 unsigned long fint, clkdco, clkout; in hdmi_pll_compute() local
79 clkout = clkdco / m2; in hdmi_pll_compute()
86 DSSDBG("Fint %lu, clkdco %lu, clkout %lu\n", fint, clkdco, clkout); in hdmi_pll_compute()
96 pi->clkout[0] = clkout; in hdmi_pll_compute()
/Linux-v5.10/drivers/clk/renesas/
Dr9a06g032-clocks.c133 D_ROOT(CLKOUT, "clkout", 25, 1),
135 D_FFC(CLKOUT_D10, "clkout_d10", CLKOUT, 10),
136 D_FFC(CLKOUT_D16, "clkout_d16", CLKOUT, 16),
137 D_FFC(CLKOUT_D160, "clkout_d160", CLKOUT, 160),
138 D_DIV(CLKOUT_D1OR2, "clkout_d1or2", CLKOUT, 0, 1, 2),
139 D_FFC(CLKOUT_D20, "clkout_d20", CLKOUT, 20),
140 D_FFC(CLKOUT_D40, "clkout_d40", CLKOUT, 40),
141 D_FFC(CLKOUT_D5, "clkout_d5", CLKOUT, 5),
142 D_FFC(CLKOUT_D8, "clkout_d8", CLKOUT, 8),
143 D_DIV(DIV_ADC, "div_adc", CLKOUT, 77, 50, 250),
[all …]
/Linux-v5.10/drivers/gpu/drm/omapdrm/dss/
Dpll.c260 * for clkout. Additionally clkdco rate will be the same as clkout rate
261 * when clkout rate is >= min_clkdco.
264 * clkout = clkdco / m2
269 unsigned long fint, clkdco, clkout; in dss_pll_calc_b() local
275 DSSDBG("clkin %lu, target clkout %lu\n", clkin, target_clkout); in dss_pll_calc_b()
301 clkout = clkdco / m2; in dss_pll_calc_b()
308 DSSDBG("Fint %lu, clkdco %lu, clkout %lu\n", fint, clkdco, clkout); in dss_pll_calc_b()
318 cinfo->clkout[0] = clkout; in dss_pll_calc_b()
/Linux-v5.10/Documentation/devicetree/bindings/net/can/
Dcc770.txt24 - bosch,clock-out-frequency : slock frequency in Hz on the CLKOUT pin.
25 If not specified or if the specified value is 0, the CLKOUT pin
28 - bosch,slew-rate : slew rate of the CLKOUT signal. If not specified,
Dsja1000.txt41 - nxp,clock-out-frequency : clock frequency in Hz on the CLKOUT pin.
42 If not specified or if the specified value is 0, the CLKOUT pin
/Linux-v5.10/Documentation/devicetree/bindings/clock/
Dcirrus,lochnagar.yaml48 - ln-cdc-clkout # Output clock from CODEC card.
49 - ln-dsp-clkout # Output clock from DSP card.
57 - ln-spdif-clkout # Optional input clock from SPDIF.
Dbaikal,bt1-ccu-pll.yaml60 +---+ +->+---+ +---+ /->+---+ | |--->CLKOUT
71 divider, NF - PLL clock multiplier, OD - VCO output clock divider, CLKOUT -
77 The PLLs CLKOUT is then either directly connected with the corresponding
/Linux-v5.10/drivers/net/can/cc770/
Dcc770_platform.c119 priv->clkout |= (cdv - 1) & CLKOUT_CD_MASK; in cc770_get_of_node_data()
133 priv->clkout |= (slew << CLKOUT_SL_SHIFT) & in cc770_get_of_node_data()
152 priv->clkout = pdata->cor; in cc770_get_platform_data()
207 "bus_config=0x%02x clkout=0x%02x\n", in cc770_platform_probe()
209 priv->cpu_interface, priv->bus_config, priv->clkout); in cc770_platform_probe()
/Linux-v5.10/Documentation/devicetree/bindings/clock/ti/
Dadpll.txt27 "481c5040.adpll.clkout",
39 "481c5080.adpll.clkout",
/Linux-v5.10/drivers/rtc/
Drtc-rv3028.c655 int clkout, ret; in rv3028_clkout_recalc_rate() local
658 ret = regmap_read(rv3028->regmap, RV3028_CLKOUT, &clkout); in rv3028_clkout_recalc_rate()
662 clkout &= RV3028_CLKOUT_FD_MASK; in rv3028_clkout_recalc_rate()
663 return clkout_rates[clkout]; in rv3028_clkout_recalc_rate()
722 int clkout, ret; in rv3028_clkout_is_prepared() local
725 ret = regmap_read(rv3028->regmap, RV3028_CLKOUT, &clkout); in rv3028_clkout_is_prepared()
729 return !!(clkout & RV3028_CLKOUT_CLKOE); in rv3028_clkout_is_prepared()
754 init.name = "rv3028-clkout"; in rv3028_clkout_register_clk()
Drtc-rv3032.c564 int clkout, ret; in rv3032_clkout_recalc_rate() local
567 ret = regmap_read(rv3032->regmap, RV3032_CLKOUT2, &clkout); in rv3032_clkout_recalc_rate()
571 if (clkout & RV3032_CLKOUT2_OS) { in rv3032_clkout_recalc_rate()
572 unsigned long rate = FIELD_GET(RV3032_CLKOUT2_HFD_MSK, clkout) << 8; in rv3032_clkout_recalc_rate()
574 ret = regmap_read(rv3032->regmap, RV3032_CLKOUT1, &clkout); in rv3032_clkout_recalc_rate()
578 rate += clkout + 1; in rv3032_clkout_recalc_rate()
583 return clkout_xtal_rates[FIELD_GET(RV3032_CLKOUT2_FD_MSK, clkout)]; in rv3032_clkout_recalc_rate()
702 init.name = "rv3032-clkout"; in rv3032_clkout_register_clk()
/Linux-v5.10/Documentation/devicetree/bindings/arm/samsung/
Dpmu.yaml58 List of clock names for particular CLKOUT mux inputs
62 pattern: '^clkout([0-9]|[12][0-9]|3[0-1])$'
/Linux-v5.10/drivers/clk/ti/
Dclk-814x.c81 "pll040clkout", /* MPU 481c5040.adpll.clkout */
82 "pll290clkout", /* DDR 481c5290.adpll.clkout */
Dadpll.c389 * about the DCO clock and not CLKOUT you can clear M2PWDNZ before enabling
570 /* Setting PLL bypass puts clkout and clkoutx2 into bypass */
666 /* Internal fixed divider, after M2 before clkout */ in ti_adpll_init_children_adpll_s()
673 /* Output clkout with a mux and gate, sources from div2 or bypass */ in ti_adpll_init_children_adpll_s()
675 ADPLL_CLKCTRL_CLKOUTEN, "clkout", in ti_adpll_init_children_adpll_s()
757 /* Output clkout, sources M2 or bypass */ in ti_adpll_init_children_adpll_lj()
759 ADPLL_CLKCTRL_CLKOUTEN, "clkout", in ti_adpll_init_children_adpll_lj()

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